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研究生:王度智
研究生(外文):Tu-Chih Wang
論文名稱:低功率移動估計器晶片設計
論文名稱(外文):Low Power Motion Estimation Chip Design
指導教授:陳良基陳良基引用關係
指導教授(外文):Liang-Gee Chen
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:英文
論文頁數:80
中文關鍵詞:低功率移動向量估計視訊壓縮架構
外文關鍵詞:low powermotion estimationH.263MPEG4video compressionarchitecture
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移動向量估計在目前的影像壓縮標準之中,始終佔了絕大部份的比例。為了要能實現移動向量估計演算法中龐大的資料運算量以及龐大的資料傳輸頻寬,已經有許多的架構被提出。但是大部份的架構都只關心資料流和運算單元的使用率問題,比較少架構考慮到功率的問題。在攜帶式的電子用品上,由於供電的電池都有一定的容量,因此功率消耗在這些電子用品上是很重要的問題。這篇論文就提出了一個256個運算單元的低功率架構來提供一個解決方法。
這個架構藉由在架構層次的分析,找出一個減少管線暫存器和降低電路切換機率的作法,再利用資料緩衝區的設置,使此架構對外的傳輸頻寬降低。這些節省造成功率的減低和晶片面積的下降。
隨著影像壓縮標準的進步,新的影像壓縮標準有越來越多的移動估計模式。像8x8區塊估計向量模式或者是PB frame模式,true B frame模式,在新一代的影像壓縮標準,像H.263+ 和MPEG-4都有這些模式存在。這個架構在設計的時候,就有將這些模式考慮在其中,此架構可以同時算出四個8x8區塊移動向量和一個16x16的區塊移動向量。而且在設計時就為了雙向移動估計設計了兩個畫面資料緩衝區。
在資料緩衝區的設計方面,此架構非常有效率的應用緩衝區,使緩衝區的大小縮小到4/3個搜尋範圍大小,而記憶體頻寬的使用縮小到四倍亮度畫面的頻寬。
在實作方面,使用了TSMC 0.35um 1P4M製程,晶片大小為4.6x4.6mm2,在操作於3.3伏特,50MHz下,消耗177mW。在此速度下,可做到CIF 60個畫面的全雙向移動估計。

In this thesis, we propose a low-power architecture for Full-Search Block-Match Algorithm (FSMBA). Motion estimation algorithm is the most computation intensive part in the video coding system, and FSBMA is the optimal solution in motion estimation algorithm. In order to handle the huge amount of data-transfer and computation, various architectures have been proposed. But most of these architectures do not have the consideration of power consumption. This proposed 256-PE architecture provides low switch probability, less pipeline register while maintaining the same critical path, and low external-memory bandwidth requirement. Therefore, it has better power performance in the architecture level.
When the video coding has technology advanced, there are more functions needed in the new video-coding standard, such as AP mode, PB-frame mode, and true B frame mode. They are also considered in the purposed architecture. It has 2 previous frame buffer and calculates 4 AP mode vectors and 1 normal mode vector concurrently.
For the purpose of decreasing the external-memory bandwidth, an efficient previous data buffer is proposed. The size of this buffer is optimized for search range of -16 to +15, which is normally used in the video standard. The external-memory bandwidth can be reduced to 4 luminance pixel rate (3 luminance pixel rate for previous data, 1 luminance pixel rate for current data). This scheme uses small amount of memory to achieve this low external memory bandwidth.
In order to integrate motion estimation of the whole codec system, it is important to design a good interface with other parts in the system. This design also implements an interface with DSP and has some programmability.

Abstract
Chapter 1. Introduction
Chapter 2. Previous Architecture of Motion Estimation
Chapter 3. Power Analysis of Motion Estimation
Chapter 4. Proposed Architecture
Chapter 5. Implementation
Chapter 6. Conclusion
Bibliography

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