臺灣博碩士論文加值系統

本文係利用壓阻材料受應力時會改變阻值的特性，以MOS製程設計並製作壓阻式應變計於待封裝晶片上，量取晶片於封裝過程的應力及溫度變化。
文中將先利用測試樑，校正晶片的壓阻係數及電阻溫度係數，以校正後的壓阻係數、電阻溫度係數及晶片上應變計於封裝過程量得的訊號，求出晶片於封裝過程中的應力及溫度分布。
文中將詳細推演計算公式至可數值運算，並配合計算公式設計測試樑及晶片上壓阻應變計排列之角度，最後實作出測試樑及晶片作實驗，量取晶片的壓阻係數和電阻溫度係數及封裝時的應力和溫度分布。

Changes in stress and temperature caused by microchip packaging are studied. Piezoresistive strain gauges are fabricated onto a chip prior to packaging, and used to measure the resulting stress and temperature.
A test bar is used to determine the piezoresistance coefficients and the temperature coefficients of resistivity of the wafer. Then the characterized strain gauges are used to measure the data.
An algorithm for determining the orientation of the strain gauges is demonstrated. The test bar and chip are fabricated and tested. The piezoresistance coefficients and temperature coefficients of resistivity of the test bar, and the stress and temperature on the chip during packaging is obtained.

第一章、緒論 1
1.1前言 1
1.2文獻回顧 2
1.3本文目的與內容簡介 3
第二章、理論推導 5
2.1壓阻性質 5
2.1.1單晶矽的機械性質 5
2.1.1.1虎克定律及減縮指標 5
2.1.1.2楊氏模數、剪力模數及波桑比 8
2.1.1.3任意方向的應力及應變 9
2.1.2壓阻的機電性質 10
2.1.2.1壓阻係數 10
2.1.2.2單晶矽的壓阻係數 14
2.1.2.3任意方向的壓阻係數15
2.1.3壓阻的電阻值 16
2.2校正公式 18
2.2.1壓阻係數的校正 18
2.2.2量取應變 22
2.2.3壓阻排列角度的校正 27
2.2.4由惠斯同電橋量出壓阻的變化 28
第三章 實驗設計及步驟 29
3.1實驗設計 29
3.1.1步驟一 29
3.1.2步驟二 30
3.2晶片設計 30
3.2.1步驟一 30
3.2.2步驟二 30
3.3晶片製造 31
3.4電路設計 32
3.4.1 打線 32
3.4.2 焊接 32
3.4.3 惠斯同電橋 32
3.4.4 頻道切換 32
3.4.5 訊號放大 33
3.4.6 類比/數位 轉換 33
3.5實驗設備 33
3.6實驗步驟 34
3.6.1事前準備 34
3.6.2實驗步驟 38
3.6.2.1步驟一 38
3.6.2.2步驟二 38
第四章 結果及討論 40
4.1計算過程 40
4.2結果 41
4.3討論 42
第五章 結論與建議 44

[1] Charles S. Smith, “Piezoresistance Effect in Germanium and Silicon”, Physical Review, Vol. 94, pp.42-49, 1954
[2] W.P. Mason and R.N. Thurston, "Use of Piezoresistive Materials in the Measurement of Displacement, Force, and Torque", Journal of the Acoustical Society of America, Vol. 29, No. 10, pp.1096-1101, October 1957
[3] O.N. Tufte and E.L. Stelzer, “Piezoresistive Properties of Silicon Diffused Layers”, Journal of Applied Physics, Vol. 34, No. 2, pp.313-318, February 1963
[4] Yozo Kanda, “A Graphical Representation of the Piezoresistance Coefficients in Silicon”, IEEE Transactions on Electron Devices, Vol. ED-29, No.1, January, pp.64-70, 1982
[5] Kazuji Yamada, Motohisa Nishihara, Satoshi Shimada, Masanori Tanabe, Michitaka Shimazoe, and Yoshitaka Matsuoka, “Nonlinearity of the Piezoresistance Effect of p-Type Silicon Diffused Layers”. IEEE Transactions on Electron Devices, Vol. ED-29, No. 1, pp.71-77, January 1982
[6] H.C.J.M. Van Gestal, A. Bossche, and J.R. Mollinger, "On-Chip Piezoresistive Stress Measurement in Three Directions", Sensors and Actuators A., Vol. 25-27, pp.801-807, 1991
[7] Richard C. Jaeger, Jeffrey, Martin T. Carey, and R. Wayne Johnson, “Off-Axis Sensor Rosettes for Measurement of the Piezoresistive Coefficients of Silicon”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 16, No. 8, pp.925-931, 1993
[8] 童若峻，壓阻式微型加速度計之設計與製造，國立台灣大學機械工程研究所碩士論文, 1995
[9] J.J. Wortman and R.A. Evans, “Young’s Modulus, Shear Modulus, and Poisson’s Ratio and Germanium”, Journal of Applied Physics, Vol. 36, No. 1, pp.153-156, January 1965
[10] 林容生，半導體感測器壓阻形狀之最佳化設計，國立台灣大學機械工程研究所博士論文, 1998
[11] J.T.L. Thong, W.K. Choi, C.W. Chong, “TMAH etching of silicon and the interaction of etching parameters ”, Sensors and Actuators A, Vol. 63, No. 3, pp.243-249, Dec 1997