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研究生:陳均煒
研究生(外文):Jung-Wei Chen
論文名稱:多階層式資料壓縮晶片架構設計
論文名稱(外文):The design of multilevel data compression chip architecture
指導教授:林銘波林銘波引用關係
指導教授(外文):Ming-Bo Lin
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:55
中文關鍵詞:多階層式壓縮lzwhuffman架構
外文關鍵詞:multilevel compressionlzwhuffmanarchitecture
相關次數:
  • 被引用被引用:2
  • 點閱點閱:270
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文提出一個新的多階層式硬體壓縮架構,使用0.7K bytes記憶體,達到和動態霍夫曼演算法相同的壓縮率。新架構以LZW和霍夫曼演算法為基礎,修改成為適合硬體的架構。在LZW演算法上,修改記憶體配置方式並將處理單位由字組改為字串,提升解壓縮時的處理速度。霍夫曼演算法上的修改,則以一個排序串列取代原有的樹狀結構做動態調整,降低硬體需求以及提高輸出入壓縮碼的處理速度。
結合LZW高速壓縮解壓縮和霍夫曼碼可變動長度壓縮碼的特點,以新架構和動態霍夫曼演算法比較,有相同的壓縮率,而只需要使用一半硬體資源,壓縮速度則是每次輸出一個壓縮碼比上動態霍夫曼演算法每次一個位元。
In this thesis, we propose a new multilevel hardware architecture that combines the features of both dynamic Huffman algorithm and LZW algorithm. In particular, the memory allocation and the data unit of compression is changed from byte, used by LZW algorithm, to byte stream. In addition, the tree-based dynamic update method used in dynamic Huffman algorithm is changed to an order list for speeding up the compressing rate. The resulting architecture shows that it can reach the same compression ratio as dynamic Huffman algorithm but only at the cost of one-half hardware resource. Furthermore, the compressing data rate is one codeword per cycle rather than one bit per cycle.
1.1 簡介 1
1.2 壓縮的種類 2
1.3 各章節介紹 5
第二章 相關研究 6
2.1 霍夫曼演算法(Huffman algorithm) 6
2.2 動態霍夫曼演法(Dynamic Huffman algorithm) 9
2.3 LZW演算法 11
2.4 WDLZW演算法 15
2.5 演算法比較 16
第三章 新的多階層式壓縮架構 18
3.1 PD-LZW演算法 18
3.2 AHAT演算法 21
3.3 canonical 霍夫曼碼 23
3.4 架構比較 26
第四章 硬體架構與模擬 28
4.1 PD-LZW 架構 29
4.1.1 輸入控制單元 29
4.1.2 字典 32
4.1.3 輸出控制單元 33
4.2 AHAT架構 37
4.2.1 排序串列 38
4.2.2 輸入控制交換單元 38
4.2.3 輸出控制單元 42
4.3 系統模擬 46
4.3.1 CAM 46
4.3.2 PD-LZW模擬結果 47
4.3.3 AHAT模擬結果 50
第五章 結論 53
參考文獻 54
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[11] Gallager, R.G., "Variation on a theme by Huffman," IEEE Trans Information Theory, IT-24, 1978, pp. 668-674.
[12] Witten, I.H., Moffat, A., Bell, T.C., "Managing Gigabytes Compressing and Indexing Documents and Images," Chapter 2, 1994.
[13] Jiang J., Jones S., "Word-based dynamic algorithm for data compression," IEE Proceedings-I, Vol.139, No.6, Dec., 1992, pp. 582-586.
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[1] Sheng-Lung Ho, A Data Compression Hardware Architecture Design Based-on LZW Algorithm, 碩士論文-國立臺灣工業技術學院工程技術研究所, June, 1994.
[18] L.-Y.Liu, J.-F.Wang, R.-J.Wang, J.-Y.Lee, "Design and hardware architecture for dynamic Huffman coding," IEE Proc.-Comput. Digit. Tech., Vol.142, No.6, Nov., 1995, pp. 411-418.
[19] Ming-Bo Lin, Yung-Sen Chen, "A priority-output CAM for the PDLZW data compression algorithm," The 8th VLSI Design/CAD Symposium, August 21-23, 1997, Taiwan, pp. 341-344.
[20] Ming-Bo Lin, "A parallel VLSI architecture for the LZW data compression algorithm, " International Symposium on VLSI Technology, Systems, and Applications, June 3-5, 1997, Taiwan, pp. 98-101.
[21] Yung-Sen Chen, The Design and Implementation of a Data Compression Chip Based-on LZW Algorithm, 碩士論文-國立臺灣工業技術學院電子工程技術研究所, June, 1997.
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