硬體式的BP神經網路處理器通常遭遇到輸出入資料格式處理不便、演算法固定不易修改等問題。而軟體式的BP神經網路處理器，可能會花費太多的時間在連結權重的計算上，而沒有良好的效能。因此本論文係關於軟硬整合式BP神經網路處理器的設計與實作，其中由硬體和軟體兩部份的模組所構成，硬體模組是採用單指令多資料流心跳式陣列處理器(SIMD-Systolic Array Processor)，軟體模組則是採用C++程式語言撰寫而成。
在處理的過程中。首先，軟體模組將大型的矩陣運算分割成16×16的單位矩陣送入硬體模組中。運算完成後，硬體模組將結果傳回系統記憶體中。最後，由軟體模組修正神經網路的連結權重。

Usually, a hardware-based BP neural net processor suffers from some problems such as the inconvenience of data formats and the difficulty of modifying the algorithm, and a software-based BP neural net processor may consume too much computing time to have a real-time response. Therefore , this thesis is related to the design and implementation of a BP neural net processor which consists of both hardware and software modules. The hardware module is a SIMD-Systolic matrix processor and the software module is a C++ program running on personal computer.
During processing, first, the software module partitions large matrix operations into 16×16 units and send them to the hardware module through PCI interface. After finishing the matrix computation, the hardware module returns the result to the system memory. Finally, the software module update the connection weights for the BP neural net.
1.1 研究動機
1.2 研究背景
1.3 論文組織及概觀
Ch2.系統架構
2.1 系統方塊圖
2.2 硬體模組介紹
2.3 軟體模組介紹
Ch3.硬體模組驅動程式
3.1 MS-Windows Driver Architecture
3.2 PCI介面卡
3.3 Design of Bus Master DMA Driver
3.4 矩陣運算的前置處理
3.5 VxD和DLL的連結
Ch4.BPN軟體處理模組
4.1 神經網路簡介
4.2 BP神經網路的模型推導
4.3 BP神經網路的演算法
4.4 BP神經網路訓練方法的改良
4.5 BPN軟體處理模組
4.6 BPN神經網路處理器介面
Ch5.結論
5.1 測試與分析
5.2 未來展望
參考文獻
作者簡介

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