|
[1] Behzad Razavi, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits─A Tutorial” [2] Vincent von Kaenel, Daniel Aebischer, Christian Piguet, and Evert Dijkstra, “ A 320MHz, 1.5mW @ 1.35V CMOS PLL for Microprocessor Clock Generation,” IEEE J. Solid-State Circuits, vol. 31, pp. 1715-1722, Nov. 1996. [3] FLOYD M. GARDNER, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Comm., vol. COM-28, pp. 1849-1858, Nov. 1980. [4] Neil H.E. Weste, and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, 2nd ed., Addison-Wesley, 1993. [5] Qiuting Haung, and Robert Rogenmoser, “Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single- Phase Clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-465, March 1996. [6] Behzad Razavi, “A Study of Phase Noise in CMOS Oscillators,”IEEE J. Solid-State Circuits, vol 31, pp. 331- 343, March 1996. [7] JIREN and CHRISTER SVENSSON, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62- 70, Feb. 1989. [8] Roland E. Best, Phase-Locked Loops : theory, design, and applications, 2nd ed., McGraw-Hill, 1993.
|