臺灣博碩士論文加值系統

本研究主要是將Charge-Pump PLL的model[2]加以修改，使之適用在時脈產生器電路上。其中，我們以實際的電路來驗證此理論的可行性。而此鎖相迴路(PLL)的實際參數包括充電泵(charge-pump)的充放電流(IP)、迴路濾波器(loop filter) 的電阻(R)電容(C)、電流控制振盪器(current control oscillator)的增益(Kv)及除頻器(divider)除數(N)的設計，皆可利用我們所推導的鎖相迴路系統穩定性與過載圖來達成。此顆時脈產生器是採用0.6um SPTM的製程來研製晶片，它可產生64MHz的clock信號，鎖定時間25us，電流控制振盪器的振盪頻率可由120MHz變化到320MHz。本電路最大功率消耗約為40mW，晶片面積約520um650um。

In this paper, we make some modifications in the original model of the charge-pump phase locked loop (PLL) and apply this modified model into the clock generator circuit. We also present the result of the practical circuit designed in this manner to verify this modified model. The parameters of this PLL circuit include : the charge pump current (Ip), resistor (R) & capacitor (C) values of the loop filter, the gain (Kv) of the current-controlled oscillator (CCO) and the N-number of the divider. All of the parameters mentioned previously can be implemented by the derived stability and overload figure of our PLL system. This PLL chip is fabricated by 0.6um SPTM process, and it can generate 64MHz clock signal with 25us of locked time. The oscillating frequency range of the CCO is from 120MHz to 320MHz. In this chip, the maximum power dissipation is about 40mW, and the area is about 520um650um.

第一章 緒論 1
1.1 研究背景及目的 1
1.2 大綱 2
第二章 充電泵鎖相迴路 3
2.1 系統簡介 3
2.1.1 相位頻率偵測器 4
2.1.2 充電泵與迴路濾波器 6
2.1.3 壓控振盪器 6
2.2 系統分析與模擬 7
2.2.1 系統分析 7
2.2.2 二階充電泵鎖相迴路 9
2.2.3 系統暫態模擬 16
第三章 時脈產生器的系統分析 19
3.1 架構簡介 19
3.2 系統分析 20
3.3 探討 22
3.4 系統模擬 23
第四章 時脈產生器的設計與模擬 25
4.1 相位頻率偵測器 26
4.2 充電泵與迴路濾波器 31
4.3 電流控制式振盪器 34
4.4 除頻器 38
4.5 時脈產生器完整電路佈局圖 43
第五章 測試結果與驗證 45
5.1 電流控制振盪器測試結果 46
5.2 除頻器測試結果 50
5.3 時脈產生器的整體測試結果 53
5.4 自然頻率(nature frequency)及阻泥因子(damping factor)
之量測 56
第六章 結論 64
參考文獻 66

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