臺灣博碩士論文加值系統

隨著元件體積的縮小、操作速度的增加，在電子電路系統中，來自元件本身，以及來自系統之外的電磁干擾污染日趨嚴重。尤其是在高速、低電壓元件或系統的正常工作能力可能受電源端進入的干擾雜訊影響。另一方面，電磁放射的要求也日趨嚴格。這些使得電子電路的設計者，不能再把電磁相容的問題等閒視之。假設電磁干擾訊號從不同的路徑耦合進入CMOS收發器，本論文探討了不同的干擾途徑影響元件對電磁干擾的感受度；負載效應的影響在本文中亦有所探討。此外，初步模擬結果與實驗相去甚多，我們試從積體電路的佈局與結構出發，以SPICE模型輔助模擬實驗，探討電路中電磁干擾與各組件的關係，改善模擬程式，以期模擬結果可以說明實驗的結果。CMOS閘極多晶矽與金屬覆線間電容的電磁干擾效應，將作進一步的探討。

As a device scales down and speeds up, the electromagnetic in-terference pollution coming from the device itself and from the envi-ronment can be much more severe. Especially, in a low-voltage and high-speed system, its performance is influenced by the interference noise conducted from the power supply. On the other hand, the elec-tromagnetic emission limit becomes tight. Thus, the electromagnetic compatibility becomes essential. Assuming that the electromagnetic interference signal couples into a CMOS transceiver, device suscepti-bility to electromagnetic interference is presented in this thesis. The influence of loading effect is also presented. Besides, the relationship between individual components and the electromagnetic interference effect are studied, based on the IC layout and device structure. A simulation method is presented to explain experimental data. Further-more, the role of routing capacitance between the metallization and poly-silicon on electromagnetic effect is investigated.

目 錄
中文摘要I
英文摘要II
誌 謝III
目 錄IV
圖 例VII
第一章 緒論1
1.1 前言1
1.2 電磁相容性2
1.2.1 EMI發生之原因2
1.2.2 電磁干擾的傳播路徑方式3
（一）輻射性干擾3
（二）傳導性干擾4
（三）複合式干擾4
1.3 研究動機4
1.4 章節簡介5
第二章 CMOS邏輯電路特性6
2.1 CMOS的基本結構與操作原理6
2.2 CMOS反相器的基本特性9
2.2.1 臨界電壓(Threshold Voltage)9
2.2.2 雜訊邊限(Noise Margins，NM)10
2.2.3CMOS邏輯電路開關特性10
2.3 CMOS IC電路常見之雜訊干擾14
第三章 CMOS收發器電磁干擾的途徑分析15
3.1 CMOS三態閘15
3.2 經由電源端途徑干擾之影響19
3.2.1 負載電容對靜態平均輸出位準之影響19
3.2.2 負載電容對動態輸出特性之影響22
3.2.3 負載電阻對靜態平均輸出位準之影響22
3.2.4 負載電阻對動態輸出特性之影響26
3.3 經由輸入端途徑干擾之影響26
3.3.1 負載電容對靜態平均輸出位準之影響26
3.3.2 負載電容對動態輸出特性之影響29
3.3.3 負載電阻對平均輸出電壓位準之影響29
3.3.4 負載電阻對動態輸出特性之影響29
3.4 結果討論34
第四章 輸出到輸入電容Cm對CMOS 收發器的電磁干擾效應之影響35
4.1 輸出到輸入電容Cm35
4.2 CMOS閘的Cm電容值預估36
4.3 Cm電容在CMOS收發器受電源端雜訊干擾，對平均輸出電壓位準的影響40
4.3.1 量測與模擬系統40
4.3.2 直流轉換曲線40
4.3.3 平均輸出位準受干擾訊號功率的影響46
4.3.4 平均輸出位準受干擾訊號頻率的影響48
4.3.5 平均輸出電壓位準受干擾訊號耦合相位的影響52
4.3.6 平均輸出電壓位準受Cm電容的影響58
4.3.7 結果討論60
4.4 Cm電容對CMOS收發器受電源端雜訊干擾動態輸出特性的效應分析61
4.4.1 量測與模擬系統61
4.4.2 Cm電容對輸出訊號上升時間受干擾雜訊的影響61
4.4.3 Cm電容對輸出訊號下降時間受干擾雜訊的影響67
4.4.4 Cm電容對輸出訊號延遲時間受干擾雜訊的影響70
4.4.5 Cm電容對輸出訊號脈波寬度受干擾雜訊的影響73
4.4.6 結果討論77
第五章 結論78
參考文獻80
作者簡介84

[1] 莊達人, VLSI製造技術, 高立圖書有限公司, pp.5-6, 1997。
[2] 陳柏宏, 電磁干擾與防止對策, 許正道發行, 1996。
[3] 林國榮, 電磁干擾及控制, 全華科技圖書股份有限公司, pp 4-5, 1987。
[4] 葉中雄,曾衍彰, 電磁干擾與防護, 徐氏基金會, pp12-14, 1988。
[5] C. K. Liu, "Analytic Nonlinear Model for Harmonics Analysis in CMOS Inverters," IEEE Transactions on Cir-cuits and Systems-I: Fundamental Theory and Applica-tions, Vol. 45, No. 7, pp. 741-745, July 1998.
[6] C. K. Liu, W. D. Yang, T. P. Jou, F. S. Lai and J. M. Chen, "EMI Effects on MOSFETS and CMOS Inverters and Their Predictions," Journal of the Institute of Engineers, Vol. 21, No. 2, pp. 129-138, 1998.
[7] 呂文超，CMOS積體電路電磁干擾影響之研究，碩士論文，國立台灣科技大學，1998。
[8] 周宗平，CMOS閘的電磁干擾分析，碩士論文，國立台灣工業技術學院，1995。
[9] 張哲彰，CMOS反相閘的電磁干擾分析，碩士論文，國立台灣工業技術學院，1996。
[10] C. K. Liu and C. J. Ho, "Frequency Dependence of AC-interference Susceptibility in Digital ICs," IEE Pro-ceedings-Science, Measurement, and Technology, vol.142, pp. 183-188, 1995.
[11] G. Masetti, S. Graffi, D. Golzio, and Zs. M. Kovacs-V., "Failures Induced on Analog Integrated Circuits by Conveyed Electromagnetic Interferences: a Review," Microelectron. Reliab., vol. 36, No.7/8, pp. 955-972, 1996.
[12] J. J. Whalen, "Computer-Aided Analysis of RFI Effects in Digital Integrated Circuits," IEEE Transactions on Electromagnetic Compatibility, vol. EMC-21, pp. 291-297, 1979.
[13] R. E. Richardson, Jr., "Quiescent Operating Point Shift in Bipolar Transistors with AC Excitation," IEEE Jour-nal of Solid-State Circuits, vol. SC-14, pp. 1087-1094, 1979.
[14] R. E. Richardson, V. G. Puglielli, and R. A. Amadri, "Microwave Interference Effect in Bipolar Transistors," IEEE Transactions on Electromagnetic Compatibility, vol. EMC-17, pp. 216-219, 1975.
[15] R. E., Richardson, Jr., "Modeling of Low Level Rectifi-cation RFI in Bipolar Circuitry," IEEE Transactions on Electromagnetic Compatibility, vol. EMC-21, pp. 307-311, 1979.
[16] C. E. Larson and J. M. Roe, "A Modified Ebers-Moll Transistor Model for RF-Interference Analysis," IEEE Transactions on Electromagnetic Compatibility, vol. EMC-21, pp. 283-290, 1979.
[17] G. Sergio, M. Guido, and G. Domenico, "New Macro-models and Measurements for the Analysis of EMI Ef-fects in 741 Op-amp Circuits," IEEE Transactions on Electromagnetic Compatibility, vol. 33, pp. 25-33, 1991.
[18] K. Grazyna and E. Frank, "Macromodeling of FET /Bipolar Operational Amplifiers," IEEE Journal of Solid-State Circuits, vol. SC-14, pp. 1083-1087, 1979.
[19] J. G. Tront, "Computer-Aided Analysis of REI Effects in Operational Amplifiers," IEEE Transactions on Elec-tromagnetic Compatibility, vol. EMC-21, pp. 297-306, 1979.
[20] P. Mattei, S. Graffi, Zs. M. Kovacs-V. and G. Masetti, "Design of Integrated BiCMOS Operational Amplifiers with Low-Probability EMI-Induced-Failures," Microe-lectron. Reliab., vol. 35, No.33, pp. 567-586, 1995.
[21] 龍贊倫，BiCMOS IC電磁干擾的研究，碩士論文，國立台灣工業技術學院，1997。
[22] 金思漢，電磁干擾對BiCMOS積體電路影響之研究，碩士論文，國立台灣科技大學，1998。
[23] A. Cappy, F. Danneville, G. Dambrine, and B. Tamen, "Noise Analysis in Devices under Nonlinear Operation," Solid-State Electronics, 43, pp. 21-26, 1999.
[24] 張博堯, CMOS電路故障分析與檢修, 全華科技圖書股份有限公司, pp.62-63, 1979。
[25] 陳宣煉,張瑞村, 邏輯設計, 全華科技圖書股份有限公司, pp.63-84, 1996。
[26] M. Shoji, CMOS Digital Circuit Technology, Prentice-Hall Inc., pp. 61-159, 1988.
[27] 張國恩, VLSI CMOS的設計原理, 松崗出版社,pp 145-146, 1987。
[28] J. P. Uyemura, Physical Design of CMOS Integrated Circuits Using L-EDITTM, PWS Publishing Company, pp.3-12~3-16, 1995.
[29] J. J. Paulos, D. A. Antoniades and Y. P. Tsividis, "Measurement of Intrinsic Capacitance of MOS Tran-sistors," ISSCC82 Digest, pp. 238-239, February 1982.
[30] J. J. Paulos and D. A. Antoniades, "Measurement of Minimum-Geometry MOS Transistor Capacitance," IEEE J. Solid-State Circuits, vol. SC-20, pp. 277-283, February 1985.