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研究生:吳柏顥
研究生(外文):Po-Hao Wu
論文名稱:16位元多級順向MASH超取樣Sigma-Delta類比數位調變器之晶片設計與實現
論文名稱(外文):A Chip Design and Implementation of 16-bit MASH Oversampling Sigma-Delta Analog-to-Digital Modulator
指導教授:吳紹懋
指導教授(外文):Sau-Mou Wu
學位類別:碩士
校院名稱:元智大學
系所名稱:電機與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:90
中文關鍵詞:超取樣類比數位交換電容雜訊移頻多級順向
外文關鍵詞:OversamplingAnalog-to-Digitalswitched capacitornoise shapingMASH
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本論文研究設計一個高解析度2階Cascaded Sigma-Delta超取樣(Oversampling)類比數位調變器晶片。
此調變器的設計是以差動交換電容電路(Fully Differential Switched Capacitor)的技術來達成,並利用超取樣率(Oversampling Ratio, OSR)、雜訊移頻(Noise Shaping)、多級順向(Multi-stage Noise Shaping, MASH)等等類比調變器設計方法,以提升整體的效能。其解析度可達16-bit之高,而信號範圍為基頻48KKHz 範圍。此一規格的調變器將可應用於AC97 (Intel Audio Codec 97) 介面中。其系統取樣頻率為12.28MHz,超取樣率為128倍,訊號雜訊比為96dB,使用±2.5V雙電源,消耗功率為19.6955mW,佈局面積為647.1μm×358.7μm,晶片面積為1800μm×1800μm,使用的製程技術為聯華積體電路製造公司(UMC) 0.5μm 2P2M製程。

In this thesis, we propose a high-resolution 2nd-order cascaded Sigma-Delta oversampling Analog-to-Digital modulator chip.
The modulator is implemented with fully differential switched capacitor circuits, over-sampling ratio, noise shaping, and multi-stage noise shaping. The modulator achieves a resolution of 16-bit and the signal bandwidth is 48KHz. The specification is fit for Intel Audio Codec 97 interface. The system is driven by 12.28MHz, and the OSR is 128, the SNR is 96.6dB the power supply is ±2.5V, the power consumption is 19.6955mW, the modulator layout area is 647.1μm×358.7μm, and the chip area is 1800μm×1800μm. The fabrication technology is UMC 0.5μm 2P2M technology.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 ix
圖目錄 x
第一章 概論 1
1.1 研究動機與背景 1
1.1.1 Intel Audio Codec 97(AC97) 3
1.2類比數位轉換器(Analog-to-Digital Converter) 5
1.2.1 一般傳統的ADC 5
1.2.2 超取樣ADC的優缺點 6
1.2.3 超取樣ADC的應用 7
1.3 論文章節編排架構 7
第二章 超取樣ΣΔADM之系統架構與原理 9
2.1 超取樣(Oversampling)定理 9
2.1.1 奈奎氏取樣率(Nyquist Rate) 9
2.1.2 量化誤差(Quantization Errors) 10
2.1.3 超取樣(Oversampling)原理與其優點 11
2.1.4雜訊移頻(Noise Shaping)技巧 12
2.1.5 數位降頻濾波器(Decimation Filter) 13
2.2 各類超取樣ADM架構的介紹 16
2.1.1 低階(Low-order)超取樣類比調變器 17
2.2.2 高階(High-order)超取樣類比調變器 19
2.2.3 多位元回授(Multi-bit Feedback)架構 20
2.2.4 多級順向(MASH)超取樣類比調變器 21
第三章 系統設計流程及行為模擬 23
3.1 研究設計流程與考量 23
3.1.1 設計流程(Design Flow) 23
3.1.2 設計考量 24
3.2多級順向超取樣類比調變器(MASH) 26
3.2.1 MASH的優缺點 26
3.2.2 MASH 1-1 演算推導 27
3.2.3一階調變器參數產生與訊號流程之行為模擬 30
3.2.4 MASH 1-1 行為模擬 33
第四章 交換電容電路高階模擬 36
4.1 交換電容電路(Switched-Capacitor, SC)原理與模擬 36
4.1.1 SC與Active RC 的比較與分析 36
4.1.2 SC電路設計 38
4.1.3 SC理想電路模擬 43
4.2 數位消弭邏輯電路(Digital Cancellation Logic, DCL)高階
模擬 45
4.2.1 DCL的工作原理 45
4.2.2 DCL 簡化設計 47
4.3 電路元件非理想模擬(nonideal simulation) 50
第五章電路設計與模擬分析 52
5.1 內建電路元件設計考量 52
5.1.1 運算放大器(OP-Amps) 52
5.1.2 類比開關電路 52
5.1.3 電容 54
5.1.4 比較器 54
5.1.5 非重疊時脈操作器(Non-overlapping Clocks Driver) 55
5.1.6 1-bit數位類比轉換器(1-bit D/A) 55
5.1.7數位消弭邏輯電路(Digital Cancellation Logic) 56
5.2 內建電路元件設計 56
5.2.1 雙端輸入信號的簡化 56
5.2.2 運算放大器(Operation Amplifiers, OP-Amps) 57
5.2.3 比較器(Comparator)與量化器(Quantizer) 62
5.2.4 類比開關(Analog Switch) 64
5.2.5 四相非重疊時脈產生器(Clock Driver) 65
5.2.6 數位消弭邏輯電路(DCL) 66
5.3 雜訊移頻(Noise Shaping)分析 67
5.4 系統電路模擬結果 70
第六章 電路實體佈局及晶片測試考量 71
6.1系統電路實體layout考量 71
6.2內建元件layout 73
6.2.1全差動式運算放大器 73
6.2.2 類比開關 74
6.2.3 全差動式比較器 74
6.2.4 一位元量化器 75
6.2.5 非重疊時脈產生電路 75
6.2.6 數位消弭邏輯電路 76
6.3 系統晶片Layout及佈局後模擬結果 77
6.4 晶片測試考量與方法 79
6.5 結語 83
第七章 結論與未來發展方向 84
7.1 結論 84
7.2 未來發展方向 84
參考文獻 86

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