臺灣博碩士論文加值系統

分時多重進接(TDMA)的系統架構已在無線行動通信領域衱採用，藉以提高
更有效的數位語音及數據服務。TDMA通道架構的優點常為了同步所須的大量
符元而失色不少。在解調器的設計中，符元同步和頻率同步是二個主要的設計
要素，藉由除去同步所須的符元，短數據群的解調處數位技術用可改善TDMA
的效率。本文研究的美國貝爾研究公司所提之個人進接通信服務(PACS)是一種
低功率微細胞行動電話系統，這系統的特性是1.8GHz的短數據群分時多工傳
輸。貝爾研究公司已發展出一套製作解調器的方法，即是經過一個模式的計算
後，同時獲得(1)符元同步，(2)偏差頻率的估計，(3)通道品質的估計。但要用該
方法時將涉及智慧財產權的問題。我們想發要一套不遜於貝爾研究公司方法。
我們所發展出的新方法，雖然符元同步及偏差頻率的估計是從二組不同的計算
獲得，而且符元同步先於偏差頻率的估計，但二組計算所須的時間總和不超過
一個數據群的時限，通道品質的估計則是計算偏差頻率的一個副產品。新方法
的計算量與貝爾實驗室的方法相似。
本論文是探討PACS系統中符元時序同步的問題，一種前置濾波器、平方
器和DFT的組合可以在30個符元時間內決定適當的取樣點。在此，我們強調的是時間同步的FPGA硬體實作，而頻率同步實作部份已在先前被發表過了。在本論文中介紹了理論分析，硬體架構、實現及印證的方法。

TDMA (time-division multiple access) architecture has been proposed for portable radio application to provide efficient digital services including voice and data application. The advantage of a TDMA channel architecture are often offset by the requirement of a significant overhead for synchronization. Two key elements in the design of a demodulator are symbol timing synchronization and offset frequency synchronization. The application of digital techniques to demodulation processing for short TDMA bursts can improve TDMA efficiency by removing the need for overhead for symbol timing and frequency offset synchronization. In this paper we studied the PACS (Personal Access Communication Service ) ,which is a low-power micro-cell mobile phone system proposed by Bellcore. The system features short-burst TDM transmission at 1.8 GHz. Bellcore has proposed a method of implementing the PACS demodulator which has been patented. The Bellcore method obtains (1)symbol synchronization, (2) an estimate of the offset frequency, and (3) the quality measure, i.e. an estimate of the channel (path) quality simultaneously after a predetermind set of computations. We develop a new method which obtains a symbol time synchronization and a frequency offset estimation through separate calculations, with symbol time estimation preceeding frequency offset synchronization. However the total of two calculations does not exceed the one data burst limit. Furthermore, the channel quality estimation is obtained as a byproduct of the frequency offset estimation. The amount of computation in this new method is comparable to that of Bellcore method.
This thesis addresses the problem of symbol time synchronization for a PACS modem. A prefilter-squarer-DFT combination is able to determine the proper sampling point within 30 symbols. The emphasis of this thesis is on hardware, in particular FPGA implementation of the symbol timing circuit. Hardware implementation of frequency synchronization circuit has been reported by another M.S. thesis advised on by Professor Fang, who also advises on this thesis. In this thesis, we first present the theory, followed by implementation methodologies, then the circuit details.

Contents
Chapter 1 Introduction…………………………………………………………….….1
Chapter 2 Symbol Time Synchronizer………………………………………………..4
2.1 Analog Square-law Symbol Time Synchronizer……………………....4
2.2 Digital Square-law Symbol Time Synchronizer……………………….8
Chapter 3 System Description and Analysis………………………………………...14
3.1 System Overview……………………………………………………14
3.1.1 Top view of PACS system architecture………………………..14
3.2 Modulator……………………………………………………………15
3.2.1 Modulation Method……………………………………………15
3.2.2 Transmitter Filter………………………………………………17
3.3 Demodulator…………………………………………………………21
3.4 Clock………………………………………………………………....22
Chapter 4 Hardware Implementation………………………………………………...25
4.1 Modulator ……………………………………………………………27
4.1.1 Serial to Parallel Converter…………………………………….29
4.1.2 Differential Phase Generator…………………………………...31
4.1.3 Raised-Cosine Filter and IF-Mixer(ROM)……………………..32
4.2 Demodulator………………………………………………………….34
4.2.1 Band-pass to Phase Converter………………………………….35
4.2.2 Symbol Timing Synchronization Estimator……………………40
4.2.3 The Delay 1/2 Bursts RAM…………………………………….46
4.2.4 Differential Phase Detection and Decision Circuit…………….47
4.3 Verification…………………………………………………………...50
Chapter5 Summary and Conclusions………………………………………………...53
References……………………………………………………………………………55

Reference
[1] "Generic Criteria for Version .1 Wireless Access Communications System(WACS)", Bellcore Technical Reference, TR-INS-001313, Issue 1, Oct 1993, Revision 1, Jun. 1994
[2] N. R. Sollenberger and J. C. I. Chuang, "Low-overhead symbol timing and carrier recovery for TDMA portable radio system," IEEE Transactions on Commun., Vol.38,NO.10.pp.1886-1892,Oct.1990.
[3] T.T. Fang, "I and Q Decomposition of Self-noise in Square-law Clock Regenerator," IEEE Transactions on Commun., Vol.36,NO9, Sept. 1988.
[4] Panayirci, E. and Bar-Ness, E.Y., "A New Approach for Evaluating the Performance of a Symbol Timing Recovery System Employing a General Type of Nonlinearity, IEEE Transactions on Commun., Vol.44, NO.1, pp.29-33, Tan.1996.
[5] F.M. Gardner, "A BPSK/QPSK Timing-error Detector for Sampled Receivers," IEEE Trans. On Commun., Vol.34, pp.423-429, May.1986.
[6] L.E. Franks and J.P. Bubrouski, "Carrier and Bit Synchronization in Data Communication," IEEE Transactions on Commun., Vol.28,pp.1107-1120,Aug.1980.
[7] Francois Patenaude and Michael L. Moher, "A New Symbol Timing Tracking Algorithm for -BPSK and -QPSK Modulations," SUPERCOMM/ICC '92. P.1588-1592 Vol.3
[8] M. Oerder and H. Meyr, "Digital Filter and Square Timing Recovery," IEEE Trans. on Commun., Vol.36,pp.605-611, May.1986.
[9] F. M. Gardner, "A BPSK/QPSK Timing-error Detector for Sampled Receivers," IEEE Trans. on Commun., Vol.36,pp.605-611,May.1988.
[10] K. Feher, Digital Communications: System and Signal Processing Techniques. Englewood Cliffs: Prentice-Hall Inc., 1987.
[11] K. Feher, Digital Communications: Satellite/Earth Station Engineering. Englewood Cliffs: Prentice-Hall Inc., 1983.
[12] Proakis, J.G., "Digital Communications", 3nd ed., McGraw-Hill, 1995.
[13] Nelson R. Sollenberger, "Pulse Design and Efficient Generation Circuits for Linear TDMA Modulation", Conf. Record IEEE VTC'90, Orlando, FL, May 6-9, 1990 pp.616-621.
[15] Albert Shyu "Computer simulation and Hardware Implementation of a Demodulator", Thesis of Master, EE, CCU, Chiayi, Taiwan Republic of China, June. 1997.
[16] Yuh-Chuan Jin "A New Symbol Time Synchronization Technique for Short-Burst TDM Transmissions", Thesis of Master, EE, CCU, Chiayi, Taiwan Republic of China, June 1997.
[17] Jan-Shin Ho "Integrated Hardware Design of a New Architecture for PACS- a Low-Power Mobile Communication System", Thesis of Master, EE, CCU, Chiayi, Taiwan Republic of China, June 1998.
[18] Jung-Chien Hsueh "IC Implementation of PACS Personal Mobile Communication System: Modulator and Demodulator Module", Thesis of Master, EE, CCU, Chiayi, Taiwan Republic of China, July 1999.