臺灣博碩士論文加值系統

雷達信號處理的特點為資料量大及對處理時間的嚴格要求。為符合雷達信號處理的需求，其硬體必需是非常有效率方能應付不斷接收到的資料量。但某些信號處理的演算法非常耗費時間，因此傳統雷達信號處理系統的作法是用一些特別設計的硬體元件來處理這些較複雜的運算，如脈波壓縮、傅立葉轉換等。 但是這種的系統設計方式雖然有運算速度較快之優點，卻也面臨了其他不利的因素。近年來隨著多用途數位信號處理器的進步，愈來愈多的信號處理系統是單純以多用途數位信號處理器來實現。
本論文提出一個以多用途數位信號處理器為基礎的多處理機雷達信號處理系統架構，並且討論其優缺點，及評估其效能。我們在此架構中使用了多級互連網路 (Multistage Interconnection Network) 來作為處理器與記憶體元件間之平行互連通道。我們也探討在各種不同互連網路架構下對整體效能的影響，並用數學分析的方法來呈現，這樣的好處是讓系統設計者在設計考量時能有效且快速地判斷。效能評估的數據顯示這樣的設計方式不僅符合計算效能之需求並可大量節省硬體設計的成本。

Radar signal processing features large quantity of data and severe timing constraints. To this end, the hardware system must be very efficient to deal with successively incoming data. Thus, traditional radar signal processing systems are generally
implemented with dedicated and proprietary hardware to deal with these complex operations, like convolution, FFT, etc. Although this type of implementation offers high-performance solution, it faces some penalties. In recent years, with the advance of general-purpose digital signal processors (DSPs), more and more signal processing systems are implemented based on DSPs. In this thesis, we present an architecture for radar signal processing systems demanding computation-intensive capability based on general-purpose digital signal processors, discuss its advantages and disadvantages, and evaluate its performance. In our architecture, we exploit multistage
interconnection network (MIN) as a fast and parallel global interconnection network between the processors and the memories. We also explore the impact of a variety of
interconnection schemes on the overall system performance.
We present an analytical study to help the system designers make correct and efficient decisions when they design the system. The results show this architecture is feasible, efficient and cost-effective.

Chapter 1 INTRODUCTION .......................................1
1.1 Motivation ...............................................1
1.2 Thesis Overiew ...........................................4
Chapter 2 GENERAL CONCEPTS ...................................5
2.1 Digital Signal Processors vs. General-Purpose Processors .5
2.2 Multiprocessor ..........................................11
Chapter 3 RADAR OPERATIONS ..................................18
3.1 Introduction to Radar ...................................18
3.2 Radar Signal Processing .................................19
3.3 System Definition .......................................21
3.4 Fast Fourier Transform (FFT) ............................25
Chapter 4 SYSTEM ARCHITECTURE................................28
4.1 System Architecture .....................................28
4.2 Evaluate the Number of Processors .......................29
4.3 Memory Elements .........................................37
4.4 Interconnection .........................................37
4.5 Control .................................................42
Chapter 5 INTERCONNECTION....................................50
5.1 Classification of Interconnections ......................50
5.2 Analytical Study of Interconnections ....................51
Chapter 6 PERFORMANCE ESTIMATION ............................59
6.1 FFT Performance .........................................59
6.2 Overall System Performance ..............................63
Chapter 7 CONCLUSION ........................................67

[1] J. L. Eaves and E. K. Reedy, Principles of Modern Radar, Van
Nostrand Reinhold, New York, 1987
[2] M. I. Skolnik, Radar Handbook, McGraw-Hill, New York, 1990
[3] M. I. Skolnik, Introduction to Radar Systems, New York, 1980
[4] N. Levanon, Radar Principles, Wiley, New York, 1988
[5] A.G. Carr, Real-time Digital Signal Processing: a Review of Applications and Technologyln, Computing & Control Engineering
Journal, vol: 1 2, March 1990, pp. 77-80
[6] G. Alberti et al, Time-domain Convolution of One-bit Coded
Radar Signals, Radar and Signal Processing, IEE Proceedings
F, vol: 138 5, Oct. 1991, pp. 438-444
[7] L. H. J. Bierens, Hardware Design for Modern Radar Process-
ing, Electronics and Communication Engineering Journal, Dec.
1997, pp. 257-270
[8] D. Camerani et al., M3: A High Performance Signal
Processor for Radar Applications, International Conference on
Application-Specific Array Processors, 1993 Proceedings, pp.
164-167
[9] J. Tulodziecki, The Application of Parallel DSP Architectures to Radar Signal Processing, Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures, IEE Colloquium on (Digest No.1995/116), pp 5/1-5/7
[10] B. Wang et al., The Design and Implementation of DSP
TMS320C40 Parallel Processing System, 3rd International
Conference on Signal Processing, vol.1, 1996, pp. 453-456
[11] http://www.ti.com, http://www.motorola.com
[12] D. Tabak, Multiprocessors, Prentice-Hall, NJ., 1990
[13] K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, 1993
[14] C. L. Wu et al., On a Class of Multistage Interconnection Networks, IEEE Transactions on Computer, vol. C-29, no. 8, Aug.
1980
[15] TMS320C6000 CPU and Instruction Set Reference Guide
(spru189d.pdf), Texas Instruments, Inc.
[16] H. S. Stone, High-Performance Computer Architecture, Addison-Wesley, Reading, MA, 1987
[17] TMS320C6000 Peripherals Reference Guide (spru190c.pdf),
Texas Instruments, Inc.
[18] Digital Signal Processors vs. Universal Microprocessors
(spra344.pdf), Texas Instruments, Inc.
[19] H. S. Stone, Introduction to Computer Architecture, Science Research Associates, 1980
[20] J. A. Fisher, Very Long Instruction Word Architectures and the ELI-512lt, Proc. 10th Symp. Computer Architecture, pp. 140-150, ACM Press, New York, 1983
[21] S. Dutta et al., K. J. O''Connor, Design Issues for Very-Long-Instruction-Word VLSI Video Signal Processors, VLSI Signal
Processing IX, IEEE Press, pp. 95-104, Oct. 1996
[22] M. J. Flynn, Some Computer Organizations and Their Effec-
tiveness, IEEE Transactions on Computer, vol. C-21, No. 9, Sep.
1972
[23] R. Duncan, A Survey of Parallel Computer Architectures, Computer vol: 23 2 , pp. 5 -16, Feb. 1990
[24] L. C. Ludeman, Fundamentals of Digital Signal Processing,
John Wiley & Sons, Inc., 1987
[25] Parallel Processing with the TMS320C4X Application Guide
(spra031.pdf), Texas Instruments, Inc.
[26] L. N. Bhuyan, Performance of Multiprocessor Interconnection
Networks, Computer, vol. 22 2 , pp. 25-37, Feb. 1989
[27] P. G. Meisl et al., Parallel Processors for Synthetic Aperture Radar Imaginglc, International Conference on Parallel Processing, 1996
[28] A. V. Oppenheim, Discrete-time Signal Processing, Prentice-
Hall, 1999
[29] J. G. Proakis, Digital Signal Processing: Principles, Algorithms, and Applications, Macmillan, 1992
[30] M. Cavadini, A High Performance Memory and Bus
Architecture for Implementing 2D FFT on a SPMD Machine,
Proceedings of IEEE International Symposium on Circuits and Systems, 1997
[31] C. P. Horne, Digital Pulse Compression, IEE Colloquium on
Solid State Components for Radar, pp. 9/1-9/6, 1988
[32] Implementing the TMS320C6201/C6701/C6211 HPI Boot
Process (spra512.pdf), Texas Instruments, Inc.
[33] TMS320C6000 Host Port to MC68360 Interface (spra545.pdf),
Texas Instruments, Inc.
[34] T. L. Casavant, Parallel Computers: Theory and Practice, IEEE Computer Society Press, Los Alamitos, Calif., 1995
[35] S. A. Felperin, Routing Techniques for Massively Parallel Communication, Proceedings of the IEEE, vo. 79 4 , pp. 488-503,
April 1991
[36] TMS320C8X System-Level Synopsis (spru113b.pdf), Texas In-
struments, Inc.