臺灣博碩士論文加值系統

本篇論文主要是提出一個整合型的電腦輔助設計方法，目的在於驗證及實現出ARM7TDMI的控制單元（Control Unit），利用驗證每一個指令集的微指令集來確認控制單元的正確性。
我們透過微指令集的流程驗證方法來協助設計者驗證針對於ARM7TDMI相容微處理器的每一個ARM指令集的微指令集，為了協助驗證的實現，我們建構了一些錯誤模式（Fault model）來偵測錯誤的發生。在這些錯誤模式環境下，我們將驗證的流程分為三個階段：單一指令驗證、管線（Pipeline）驗證、控制訊號及控制訊號值的產生以及產生控制邏輯的verilog程式；此外本程式亦會告知使用者ARM在執行兩個指令時所需要的安全管線階層（Pipe Stage），當兩指令利用資料前置（Data Forwarding）的技巧時，也會同時計算出適當的管線階層。
在資料路徑連結的驗證方面，假設每一個功能區塊（Functional Block）都是正確的，再利用測試樣品（Test Patterns）以及ARM7TDMI的指令來達成測試的目的。

This thesis proposes an integrated computer-assisted design methodology that focuses on verification and implementation of control unit of ARM7TDMI core. We address the problem of verifying the correctness of control unit by checking the micro-operations of each instruction set.
We assist the designer to verify the micro-operations of each instruction sets of a compatible ARM7TDMI microprocessor by methodology of micro-operations verification flow. To facilitate carrying out the verification, a set of fault models are created to detect the design errors. Based on these fault models, the verification process separates into three stages：single instruction and pipeline verification、control signal and control signal value creation and verilog code of control logic creation. Moreover, our program will inform user the proper pipe stage for executing two instructions by ARM. When the data forwarding is used, we also can compute the proper pipe stage.
In data path interconnection, we assume that each functional block is correct and some test patterns with instructions of ARM7TDMI are used to approach our purpose.

Chapter 1 Introduction
1.1 Motivation
1.2 Related Work
1.3 Research Scope
1.4 Research Contributions
1.5 Thesis Organization
Chapter 2 Overview of ARM7TDMI Microprocessor
2.1 ARM7TDMI Programming Model
2.1.1 Operating Modes
2.1.2 Memory Formats
2.1.3 Data Types
2.1.4 Registers
2.1.5 The Program Status Registers
2.1.5.1 The Condition Code Flags
2.1.5.2 The Condition Bits
2.1.6 Exceptions
2.2 ARM Instruction Set
2.3 Memory Interface
2.3.1 Memory Cycle Types
2.3.2 Memory Address Timing
2.3.3 Data Transfer Size
2.4 Coprocessor Interface
2.4.1 Coprocessor Present/Absent
2.4.2 Busy-Waiting
Chapter 3 Micro-Operation Verification
3.1 Single Instruction Verification
3.2 Pipelined
3.2.1 Data Hazards
3.2.2 Example for Data Hazards
3.2.3 Branch Hazards
3.3 Create Control Signal and Control Signal Value
3.4 Implementation
Chapter 4 Test Generation for Data Path
4.1 Test Pattern Generation
Chapter 5 Conclusion
Appendix

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