臺灣博碩士論文加值系統

近年來,行動電話發展極為迅速,除了高階行動電話之外,低功率.低移動性的低階行動通訊系統亦已廣為採用,其中三個主要低階的系統分別為日本的PHS,歐規的DECT,以及美規的PACS. 其中PACS與PHS系統為台灣即將在八十九年底開跑的兩大系統. 系統商分別為大眾與聯華電信,未來低功率行動電話應用的範疇主要為語音與數據傳輸的整合服務.
本論文整合無線通訊系統設計的技術,對系統時序.通道編解碼.換率塞取斗模組座良好的晶片設計. 同時對實體層之基頻模組與射頻模組的時序控制介面及實體層與聯結層之匯流排介面作一完整規劃. 最後將本晶片作語音迴路測試與兩支手機雙向通話測試,驗證多重近接(TDMA)架構之時序及通道編解螞技術的正確性.

In recent years, the development of mobile communications is growing rapidly. Besides the high-tier cellular phone, the low-tier communication system with low-power, low-mobility has been widely used. The major three low-tier systems are the Japanese PHS system, the European DECT system, and the North American PACS system. PACS system have finished design for data communication, so it can provide with voice/data integration service in the future.
The PACS is a standard adopted by ANSI for Personal Communication Systems in the United States. It is well suited to wireless local loop applications and personal communication services. It provides low-power, low-cost, high capacity, high quality, mobility, and long talk time use; also it has a rich suite of applications in urban district.
In this thesis, we integrate the wireless communication system design with Xilinx Foundation Series to develop the one-chip TDMA Controller including Channel Coding, Rate Changer, and Timing/Clock/Control sub-modules. Furthermore, we make arrangements for the timing/control interface between RF module and baseband module of physical layer, and the bus interface between physical layer and data link layer. A speech-in/speech-out loop-back-testing checks the TDMA system timing and verifies the channel coding technology by observing digital signals in the logic analyzer. Finally, we also complete the two way communication with two subscriber.

List of Figures …………..…………….……………….……….. iii
List of Tables …………..……………………...……...…………. v
1 Introduction ……………………………………………....….…… 1
1.1 System Feature and architecture .…..……….....…...…. 1
2 PACS Technical Specifications …….………..………….….…. 6
2.1 System Architecture ………..……………..……..…......… 6
2.2 Technical Characteristics ….…………………..…....…... 7
2.3 Frame Structure ………...…..………………..….…...…… 10
2.4 Burst Structure …………..……………………..…....……. 12
2.5 Synchronization ……………..………………….…........… 14
2.6 Radio Link Maintenance ……………..……………..………… 16
2.7 The Subscriber Unit Design Concept ………………..……… 17
3 System Timing and Function ………………………….......…. 20
3.1 An overview of states in the subscriber unit …………… 20
3.2 Timing Design Foundation …………………..……...…..... 21
3.3 The Function of each sub-module………..……….…...….. 24
(A) System Clock Sub-module (CLK) ………………………………. 24
(B) CCODER (Channel Coding) Sub-module …………………….…. 24
(C) CPU Sub-module ……………………………………………....… 30
(D) PCM, ADPCM Sub-module and interface …………………..... 33
3.4 The integration of each sub-module…………..37
4 System Design and Implementation .……………...…........ 39
4.1 The Subscriber Unit Architecture for PACS ……...…..… 39
4.2 Configurations of the TDMA Controller with FPGA…….... 41
4.3 Circuit Design Consideration ……..…………..……….... 43
4.3.1 Timing/Clock/Control Unit ……...…………………….… 43
4.3.2 24-bit correlator ……………………………………….... 43
4.4 Design Flow………………………………………..……………….44
4.5 Verification and Loop-back Test of DSP Module……...…. 45
4.6 Two-way Communication…………………………………………… 46
4.7 Testing Considerations………………………………….…..….47
5 Conclusion …………..…………………………………………..… 49
Appendix A Timing Simulation and Verification …………... 51
Appendix B Assembly Language Programs for 8051 CPU ….…. 53
References and Bibliography ………………..……………………. 57

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