臺灣博碩士論文加值系統

本論文中，我們提出了類神經網路求解最佳化問題之超大型積體電路設計。藉由類比積體電路平行處理的特性，可以即時處理資料，進而架構L. O. Chua所提出的非線性規劃類神經網路之模型。並利用切換電容技術來設計超大型積體電路，以實現此一特殊功能設計之智慧型晶片。
在晶片下線之前，所有電路全部經過HSPICE模擬，而且模擬結果均能夠符合設計的規格。 電路佈局完成後，必須再作DRC、ERC、LVS和LPE等等的設計準則驗證；直到所有電路的性能均可滿足系統設計的需求。晶片的製作採用聯華電子0.5 微米，雙層多晶矽雙層金屬之互補式金氧半電晶體製程，並經由HSPICE軟體做Post Layout Simulation驗證，得知所採用的理論架構與晶片Layout確實正確可行。根據電路模擬求解結果，整個電路可在 的時間（20 Clocks）即可收斂穩定，平均測試誤差約為2％，平均功率消耗僅為5mW，最高操作頻率為1MHz。

Abstract
In this thesis, we propose a Very Large Scale Integrated (VLSI) circuits design applied to optimization problems solved using Artificial Neural Networks (ANNs). According to the analog integrated circuits parallel processing performance, the L. O. Chua’s ANNs model for solving the nonlinear programming problems was constructed. Using the switched-capacitor (SC) method and VLSI fabrication technique to realize this intelligent chip was the main research aim.
Before the chip fabrication, all the function blocks have been simulated by HSPICE. The simulation results all meet the specification requirement. After accomplished circuit layout, the design criteria verification such as DRC (Design Rule Checking), ERC (Electrical Rule Check), LVS (Layout v.s. Schematic cross checking) and LPE (Layout Parameter Extraction) are made until all the performance meet the system design requirement. The chip design uses the UMC 0.5μm double-poly double-metal CMOS technology, the post layout simulation are verified by HSPICE software and the consistency between theory and layout are correct. The chip is stable in (20 clocks), the average test error is about 2％, the average power dissipation is only 5mW, and the maximum operation frequency is 1MHz.

目錄
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 x
第一章緒論 1
1.1背景 1
1.2目的 2
1.3章節介紹 3
第二章類神經網路問題求解與電路實現 4
2.1類神經網路運算法則簡介 4
2.1.1典型問題求解 4
2.1.2利用電子電路求解 5
2.1.3平衡狀態 7
2.2局部最小值問題 9
2.3電路實現 11
2.4電路實例驗證 13
第三章切換電容技術 17
3.1 MOS開關 17
3.2切換電容電路基本原理及優點 18
3.3 CMOS傳輸閘 21
第四章CMOS工作放大器設計 25
4.1摺疊式工作放大器 25
4.2摺疊式工作放大器模擬分析 28
第五章晶片實現 31
5.1晶片基本架構 31
5.2非線性電流放大器 33
5.3積分電路 34
5.4控制編碼器 35
5.5可規劃電容陣列 36
5.6二維系統求解實例 37
第六章晶片模擬與量測結果 39
6.1晶片模擬結果 39
6.2晶片量測結果 42
第七章結論 48
參考文獻 49
附錄 55

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