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研究生:謝新祥
研究生(外文):Hsieh Hsin Hsiang
論文名稱:系統整合與測試之研究
論文名稱(外文):The Study of System Integration and Testing
指導教授:金明浩金明浩引用關係
指導教授(外文):Ming-Haw Jing
學位類別:碩士
校院名稱:義守大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2000
畢業學年度:88
語文別:中文
論文頁數:80
中文關鍵詞:測試平台可程式規劃邏輯晶片軟硬體共同設計
外文關鍵詞:Test BenchFPGACodesign
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近年來,資訊界積極的發展多媒體系統及網際網路,考量資料在存送過程能正確又可靠,這方面一直需利用硬體來支援,如何有效率的發展硬體是相當重要的,在硬體發展過程中,需由演算法驗證、硬體設計、模擬驗證到功能測試中,如何提供完整的測試界面和整合環境為本案之目標。
本論文,係考量快速地發展一個原型機及其測試平台,以加速系統整合與測試之目的,本論文的研究方法係,先進行演算法分析、硬體模組製作,以CPLD建立一製作平台,各模組完成後再進行整合,整合測試之階段中再衍生自我測試、注錯和電腦界面等功能,最後,製作完成一可供展示的原型機。
對於提昇系統發展的效率的目標上,本論文提出一個具完整性和多功能的硬體發展和測試驗證支援的慨念,展現於本論文之『輔助測試發展系統』中,先運用軟硬體共同設計(Codesign)之觀念分配各功能至軟硬體和界面模組之中,節省測試和發展所需的時間。再將系統內線路設計成具重複使用性的模組或稱IP,可在其他應用上重復使用,使未來的原型系統之製作更快速。
在前述的慨念和系統的支援下,已順利完成一原型系統,可擔任監測一顆RS Code晶片的測試平台,證明此架構可提供多樣化的測試與整合功能,具有可視性、快速界面、多種工作模式等,來輔助硬體之發展和驗證。
Recently, the electronic world had paid effort on developing Multi-Media System on Internet. To get the robust information during the store and forward process has become more important. Those reliable functions on net may achieve by hardware and software. However, how to develop hardware system efficiently, from the verification of algorithm, functional simulation, the design of hardware system and verification, to offer a graceful testing environment for the support of the integration of the target system, is very important.
In the thesis, the objects of project are focusing on the developing of a prototyping system and its test platform swiftly. The research the includes the analysis of algorithm, the implementation of the hardware module, to construct a test platform. The integration of function are needed self-testing, fault injection, and the computer interface and to build up a demonstration system. With regard to the promote of the efficiency and reliability of developing a system, the thesis has bring up an ideal and resides on the target system as named as “The Testing Aid Development System”. The utilization of H/W and S/W Co-design concept has saved the time on developing and testing process. The modules of the system are constructed as reusable modules or named IPs (Intelligence Proresties), in order to speed up the developing of any prototyping system.
The thesis has already accomplished a prototyping system and used to test a RS code Chip as presented as a test bench. The prototyping demonstrates the performance on the portability, virtualization, fast interfacing, multiple modes of test etc. to assist the realization of the hardware system.
致謝………………………………………………………i
中文摘要………………………………………………..ii
英文摘要………………………………………………..iii
目錄……………………………………………………..vii
圖目錄…………………………………………………..vii
表目錄…………………………………………………..ix
第壹章 序論1
1.1問題描述2
1.2 研發上的需求3
1.3 論文架構3
第貳章 系統實現方法5
2.1發展的趨勢與方法5
2.1.1 硬體元件模組化設計5
2.1.2支援系統之界面6
2.1.3 系統之軟硬體共同發展6
2.1.4 系統之發展6
2.1.5 測試與整合7
2.2 系統發展之工具與環境8
2.2.1 軟體發展工具8
2.2.2 硬體發展工具與可規劃邏輯晶片9
2.2.3 硬體描述語言15
第參章 系統設計18
3.1系統需求18
3.2 研究方法19
3.3 系統架構設計20
3.4 軟硬體共同設計(Codesign)23
第肆章 系統發展26
4.1 演算法驗證27
4.1.1 Block Encode 與Block Decode 模組28
4.1.2 RS Code Encode 與RS Code Decode 模組31
4.1.3 EEC Interleaver 與EEC DeInterleaver 模組34
4.1.4 EFM + 與DeEFM +模組35
4.1.5 模組整合與注入錯誤36
4.2 界面設計方面37
4.2.1 界面卡1 — 使用TTL 元件38
4.2.2 界面卡2 — 使用FPGA元件41
4.3 控制模組的開發製作45
第伍章 系統整合47
5.1輔助測試發展系統之系統軟體實作47
5.2輔助測試發展系統內TBCP之硬體整合48
5.3 測試樣板之設計52
5.4 整合測試RSPC記憶體模組54
第陸章 結論與未來工作56
6.1成果56
6.2 與現有系統比較59
6.3 未來工作61
參考文獻62
附錄(Appendx)64
1.De Man, H. “System on chip Design: Impact on Education and Research”, IEEE Design and Test of Computers, July-September, 1999, pp 11-19.
2.Yarmolik, V. N., Hellebrand, S. “Symmetric Transparent BIST for RAMs”, Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings , 1999 ,pp 702 -707
3.IEEE Standard Boundary Scan 1149.1
4.Altera Corporations, “IEEE JTAG Boundary-Scan Testing in Altera Devices”, Altera Corporations conference paper, November 1998.
5.Mike wondolowsk, Adam Ley, “Boundary Scan: The Internet of Test”, IEEE Design and Test of Computers, July-September, 1999, pp 34-43.
6.Ernst, R., “Codesign of Embedded Systems: Status and Trends, ”IEEE Design & Test of Computers,” Vol 15 2, pp.45-54, April-June 1998.
7.Schulz, S.; Rozenblit, J.W.; Mrva, M.; Buchenriede, K., “Model-based codesign,” IEEE Computer, Vol 31 8, pp.60-67, Aug. 1998.
8.Navarro, S.; Gearhart, L.; Smith, G.; Schroeder, J.B. “The Integrated Diagnostic Virtual Test Bench,” AUTOTESTCON, 97. 1997 IEEE Autotestcon Proceedings, pp.683-687, 1997.
9.Edited by Janick Bergeron ,“Writing Testbenches function verification of HDL Models”.
10.洪綜懋, “The Implementation of the Test Bench for Image Compression and Coding” , 義守大學 資訊工程研究所 碩士論文, May, 1999.
11.Kevin Skahill, “VHDL FOR PROGRAMMABLE LOGIC”, ADDISON-WESLEY, 1996.
12.Altera Inc., “MAX+PLUS II VHDL”, Manual.
13.Altera Inc., “MAX+PLUS II AHDL”, Manual.
14.Edited by Jerzy Rozenbblit and Klaus Buchenrieder, “Codesign Computer-Aided Software/Hardware engineering”.
15.Daniel D. Gajski. “Essential Issues in Codesign”, IEEE Design and Test of Computers.
16.Tarek Ben Ismail and Ahmed Amine Jerraya, “Synthesis steps and Design Models for Codesign”, IEEE Design and Test of Computer, pp. 44-52.
17.P. Gillard and K. C. Posch, “A Hierarchical View of Time”, Codesign: Computer-aided Software/Hardware engineering, pp.176-189.
18.Hideki Yamauchi, Hideaki Miyakmoto, Takeshi Sakamoto, Tomofumi Watanable, Hiroyuki Tsuda and Ryuji Yamamura, “A 24X-Speed CRIC DECODER FOR A CD-DSP/CD-ROM DECODER LSI”, vol. 43, August 1997, pp. 483-490.
19.陳延華, “The Implementation of Reed-Solomon Code Using Inversionless Berlekamp Massey Algorithm”, 義守大學 資訊工程研究所 碩士論文, May, 1999.
20.Claus Schneider, Axel Jahnke, Georg Siglinfineon Technologies, Cores and Modules Munich, Germany, “A Verification Concept for Microcontroller Peripheral development and System Integration”, IEEE Fall VIUF Workshop, 1999, pp 24-29.
21.Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott, “Microprocessor Test and Test Tool Methodology for the 500MHz IBM S/390 G5 Chip”, IEEE International Test Conference, 1998, pp 717-726.
22.McGraw-Hill, Inc. “PROBABILITY, RANDOM VARIABLES, AND STOCHASTIC PROCESSES”, Third Edition, pp. 221-234.
23.Marcel Jacomet, Roger Walti, Lukas Winzenried, Jaime Perez, Martin Gysel, “Pro Test: A Low Cost Rapid Prototyping and Test System for ASICs and FPGAs”, Biel School of Engineering, MicroLab — I3S, 1997
24.DR, Marcel Jacomet, “ProTest User Manual”, Biel School of Engineering, MicroLab — I3S, Manual Version v2.1, 1998
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