臺灣博碩士論文加值系統

在這篇論文裡面，我們提出了一種應用渦輪碼及延遲處理器之多層次編碼調變系統。不同於傳統使用m個二元碼來對m層的分割結構加以編碼的方式，我們結合前m-1層一起編碼，其編碼係使用遞迴式系統性迴旋碼所裝置成的渦輪碼及串接一個延遲處理器所構成。另外在最低層上，我們再用數個擴展BCH碼來進行編碼。另配合多工器將渦輪碼加以適當交替置放在不同層次的方式，我們分別探討了三種不同架構的性能。由模擬結果顯示，在中到高訊雜比條件下，我們所建構的編碼調變系統比傳統的多層次編碼有較佳的除錯性能及較低的複雜度。

In this thesis, we propose a Turbo coded modulation scheme, the proposed coding strategy is first based on multilevel codes with interdependency between consecutive levels of a given labeling and is modified from a Turbo coded modulation [15] proposed in 1999. With m-level partition structure, we combine the first (m-1) consecutive levels as a single Turbo code, the m-th level is encoded as a BCH code. The resultant coded sequence is then sequentially processed by the multiplexer, the multilevel delay processor and the signal mapper. With proper choices of the multiplexer, the delay processor and interdependency between consecutive levels, we can design a coded modulation with good performance.
The proposed coding scheme can be suboptimally decoded in multiple stages with component codes decoded sequentally stage by stage. With some previously recovered informations, the Turbo code can be decoded by the iterative decoding, and then the BCH code can be decoded by soft-decision decoding based on ordered statistics.
With the proposed coded modulation, we show a design example for 8 PSK with code rate 2 bits/symbol. For this example, a rate 17/32 4-state Turbo code is applied to the first two levels, a (128,120,4) extended BCH code is applied to the third level, and a two-levels delay processor is applied. Simulation results show that the proposed coded modulation has some attractive performances with low decoding complexities. A BER of 10^{-5} at an E_b/N_0 of 4.4 dB can be achieved if the block length N is equal to 1024 bits.

第一章 緒綸
第二章 渦輪碼之回顧
第三章 適用於區塊碼之軟式解碼法的回顧
第四章 具延遲處理器的籬柵碼之回顧
第五章 一種應用渦輪碼及延遲處理器之多層次編碼調變 …
第六章 模擬結果及性能分析
第七章 結論
1.Introduction
2.Reviews on Turbo Codes
3.Reviews on Soft-Decision Decoding Algorithm Based on Ordered Statistics
4.Reviews on Trellis Coding Using a Delay Processor
5.Multilevel Turbo Coded Modulation Using a Delay Processor
6.Simulation Results and Performance Analysis
7.Conclusion

1. C. Berrou, A. Glavieux, and P. Thitimajshims, "Near Shannon
limit error-correcting coding and decoding : turbo-codes" in
Proc. IEEE Int. Conf. on Communications (Geneva,Switzerland,
May 1993) pp. 1064-1070.
2. C. Berrou and A. Glavieux, "Near optimum error correcting
coding and decoding: Turbo-codes," IEEE Trans. Commun. vol.44
, no.10, pp.1261-1271, Oct. 1996.
3. L. Bahl, J. Cocke, F. Jeinek, and J. Raviv, "Optimal
decoding of linear codes for minimizing symbol rate," IEEE
Trans.Inform. Theory, vol.20, pp.284-287, Mar. 1974.
4. J. Hagenauer, "Source-controlled channel coding," IEEE
trans. Commun., vol.43, no.9, pp.2449-2457, Sept. 1995.
5. J. Hagenauer, E. Offer, and L. Papke, "Iterative decoding of
binary block and convolutional codes," IEEE Trans.Inform.
Theory, vol.42, no.2, pp.429-445, Mar. 1996.