臺灣博碩士論文加值系統

隨著CMOS製程技術的發展，以及處理器運算能力的快速提升，使得許多寬頻的資料連結與傳輸技術愈來愈顯得需要。在許多的應用中，比如說多工處理器之間的連結、處理器與記憶體之間的介面、甚至於電腦與電腦之間和電腦與週邊產品的溝通，這樣子的高速介面常常扮演了非常重要的角色。也因此，有關傳輸端與接收端電路設計的一些研究目標，也從目前商品所需的數百Mb/s，延伸到下一代資料連結規格中所訂定的Gb/s的等級。這本論文的研究目的就是在設計一個可靠的介面電路，可工作在Gb/s的速度，並且試著在接收端利用一個追蹤式資料回復系統去回復所接收到的傳輸資料。
為了高速傳輸所需，設計介面電路時常常需要考慮許多取捨。同時，利用0.25-μm的製程，在2.5-V的電源電壓下，我們設計並實現了一個本研究所需的可工作在1-Gb/s的介面電路。經由Std. IEEE-1394中所訂定的4.5公尺遮蔽式雙絞線傳輸通道，這個介面電路在傳輸1.4-Gb/s的NRZ信號時，其誤碼率可以低於10-10以下。
為了把接收到的信號正確地回復成數位的資料，我們提出了一個利用數位方式回授的系統結構。利用三倍過取樣的技巧，這個追蹤式的資料回復系統可以正確地回復1-Gb/s的傳輸資料。這個系統避免了在兩倍取樣的系統中會遭遇到的亞穩態問題，並保持了閉迴路的校正特性。當取樣時脈被移至一個位元區間內時，我們把每一組的中間信號資訊直接選出來成為回復後的資料，這樣子可以減少資料選取邏輯電路的複雜度。最後，所得到的資料經過同步，則變成四組平行的輸出資料串，且速率為250-Mb/s。

The continuing scaling of CMOS process technologies, combining with the increasing computational capability of processor, indicates that high bandwidth links to communicate the information that is processed is needed. Such high-speed links are often an important part of multi-processor interconnection, processor-to-memory interfaces, and computer-to-computer or computer-to-peripheral interfaces. The research and design of transmit and receive circuits for these links target increasing link speeds from hundreds of Mb/s in current commodity link to Gb/s in the specifications for the next generation links. The goals of this research is to design a robust interface circuit with the data rate at Gb/s and try to recover the transmitted data by a tracking data recovery system at the receiving end.
For high-speed data transmission, trade—offs involved in the design of the interface should be considered. Meanwhile, the interface circuits for 1-Gb/s data rate adopted in this work have been designed and implemented with a 0.25-μm CMOS technology with a 2.5-V supply power. With a 4.5-m Shielded-Twisted-Pair cable defined in Std. IEEE-1394, the interface circuits could transmit 1.4-Gb/s NRZ signals with Bit-Error-Rate less than 10-10.
To recover the received signal to digital binary data correctly, a system architecture with a digital feedback control loop is proposed. With 3X-oversampling technique, the signal transmitted in a mesochronous system could be recovered correctly by the tracking data recovery system with the data rate at 1-Gb/s. The system prevents the metastability problem in 2X-sampling tracking systems, keeping the closed-loop phase calibration mechanism. When the sampling clock phases are moved into a bit duration, the data information sampled by the middle clock phase is picked up to be the recovered data signal, reducing the complexity of data selection logic. The recovered data would be synchronized to four channels. Using Delay-Locked Loop’s, instead of Phase-Locked Loop’s, could reduce the response time when a clock phase step is induced, and get phase-tracking rate at 1/8 of reference clock. Therefore, the input data stream at 1-Gb/s could be recovered by this system to be four parallel data at 250-Mb/s.

Acknowledgments i
Abstracts iii
Table of Contents vii
List of Tables xi
Table of Contents xiii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 CMOS Links 1
1.3 Thesis Organization 3
Chapter 2 Interface Circuits 5
2.1 Noise Considerations 5
2.1.1 Independent noise 5
2.1.2 Proportional Noise 6
2.2 Package and Channel 8
2.2.1 Basic Package Model 8
2.2.2 Channel Characteristics 9
2.3 Basic Signaling Methods 10
2.3.1 Low Impedance Signaling 11
2.3.2 High Impedance Signaling 14
2.4 Interface Circuit Design 17
2.4.1 Transmitter 17
2.4.2 Termination Method 17
2.4.3 Receiver 18
2.4.4 Simulation Results 21
Chapter 3 Background of Data Recovery System 23
3.1 Timing Margin 23
3.2 Conventional Bus Links 25
3.3 Source Synchronous Interfaces 27
3.3.1 High-Speed Buses 27
3.3.2 Point-to-Point Links 28
3.4 Serial Links 30
3.5 Timing Recovery Architectures 32
3.5.1 PLL-based timing recovery 32
3.5.2 Phase-picking-based timing recovery 37
Chapter 4 A Proposed Data Recovery System 41
4.1 Mesochronous Interconnection 41
4.2 System Architecture 42
4.3 Phase-Locked Loop and Delay-Locked Loop 45
4.4 Circuits Design 48
4.4.1 Delay-Locked Loops 48
4.4.2 Phase Selector 58
4.4.3 Phase Shifter 58
4.4.4 Control Logic 60
4.4.5 Synchronizer 61
4.4.6 System Simulation Results 62
Chapter 5 Measurement Results 67
5.1 Interface Circuit 67
5.1.1 Measurement Environment Setup 67
5.1.2 Measurement Results 68
5.1.3 Summary 69
5.2 Delay-Locked Loop’s 71
5.2.1 Measurement Environment Setup 71
5.2.2 Measurement Results 72
5.2.3 Summary 75
5.3 The Tracking Data Recovery System 76
5.3.1 Measurement Environment Setup 77
5.3.2 Measurement Results 77
5.3.3 Summary 81
Chapter 6 Conclusions and Future Works 83
6.1 Conclusions 83
6.2 Recommendations for Future Works 84
References 85

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