臺灣博碩士論文加值系統

在本篇論文中，提出了一個包含可程式化關聯器陣列架構之適用於無線通訊的數位訊號處理器。可程式化的關聯器陣列可以輕易的被設定成為slot同步器、碼群組偵測器、scrambling碼偵測器，以及RAKE接收器。此外，此關聯器也有低功率之設計。
此外，所提出的數位訊號處理器，由於其特殊之架構與指令集，在一些無線通訊標準像是GSM以及IS-95中所需之運算如Viterbi演算法以及複數運算，皆有傑出之表現。藉由和一些在無線通訊系統常用之數位訊號處理器的比較結果，可得知所提出之數位訊號處理器確實在無線通訊的演算法方面較其他數位訊號處理器來的有效率。此數位訊號處理器晶片是同時採用full-custom及cell-based的設計－在critical路徑採用full-custom，其他部份則採用0.35\mu{m}、1P4M的標準元件庫來合成。
我們相信，所提出的關聯器陣列架構以及適用於無線通訊之數位訊號處理器，在未來的第三代無線通訊行動系統設計中是非常有用的。

In this thesis, a digital signal processor that is designed for communication appli-cations
with a programmable correlator array architecture is introduced. The pro-grammable
correlator can be easily configured as a chip match filter, code group
detector, scrambling code detector, and RAKE receiver. It also has low power
consideration.
The architecture and instruction set of the proposed DSP (CDSP) makes it
has good performance at Viterbi algorithm and complex arithmetic operations for
some wireless communication standards such as GSM and IS-95. According to
the performance evaulation results, the suggested DSP core outperforms other
DSPs in terms of several operations normally used in wireless communication.
The chip was implemented in a hybrid design method where the critical path was
full-custom designed and the other parts are cell-based using a 0.35um 1P4M
cell-library.
We believe that the suggested correlator array architecture and digital signal
processor are useful for future 3G mobile terminal design.

1 Introduction 1
1.1 CDMA concepts . . ........................ 2
1.2 IMT-2000/UMTS and 3GPP .................... 2
1.2.1 3GPP . . . . ........................ 4
1.3 DSP for wireless communication system . ............. 7
1.3.1 Evolution of DSP . . .................... 7
1.3.2 Wireless communication DSPs . . ............. 10
2 3G System Architecture 17
2.1 Tri-Code Correlator . ........................ 18
2.2 Programmable Correlator Array . . . . . ............. 18
2.3 Digital signal processor . . . .................... 21
2.4 System architecture and simulation . . . . ............. 22
3 Design of communication DSP (CDSP) 25
3.1 Design Issues . . . . ........................ 25
3.1.1 Sub-Word Parallel (SWP) . . . . ............. 25
3.1.2 Channel Estimation for RAKE combining . . . ...... 26
3.1.3 Viterbi Algorithm . . .................... 26
3.1.4 FIR . . . . . ........................ 32
3.1.5 Other features ........................ 35
3.2 Instruction Set . . . . ........................ 35
3.2.1 Computational instructions . . . . ............. 36
3.2.2 Data Movement Instructions . . . ............. 36
3.2.3 Program Flow instructions . . . . ............. 36
3.2.4 Special instructions . .................... 41
3.3 Comparison . . . . . ........................ 41
3.4 Architecture Design . ........................ 41
3.4.1 ALU . . . . ........................ 44
3.4.2 CMP . . . . ........................ 44
3.4.3 MAC . . . . ........................ 47
3.4.4 SFT . . . . . ........................ 48
3.4.5 Data Memory Address Generator ............. 48
3.4.6 Program Sequencer . .................... 50
3.4.7 Interrupt and Parallel I/O port . . ............. 50
3.4.8 Booting/Testing Mode . . . . . . ............. 51
4 Design Flow and DSP Implementation 53
4.1 Design flow . . . . . ........................ 53
4.2 Hardware-C simulation . . . .................... 53
4.3 Cell-Based Design . ........................ 56
4.4 Full-Custom Design . ........................ 57
4.5 Chip Implementation ........................ 59
5 Conclusion 61

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