跳到主要內容

臺灣博碩士論文加值系統

(18.97.9.172) 您好!臺灣時間:2024/12/07 04:14
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:許正忠
研究生(外文):Cheng-Chung Hsu
論文名稱:OTA濾波電路的結構化設計與可測試性分析
論文名稱(外文):Structural Design and Testability Analysis of OTA Filter Circuits
指導教授:馮武雄馮武雄引用關係
指導教授(外文):Wu-Shiung Feng
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2000
畢業學年度:88
語文別:中文
論文頁數:98
中文關鍵詞:運算轉導放大器電壓模式電流模式多重回授迴路可控制性可觀察性可測試性內建自我測試
外文關鍵詞:operational transconductance amplifiervoltage-modecurrent-modemultiple loop feedbackcontrollabilityobservabilitytestabilitybuilt-in self-test
相關次數:
  • 被引用被引用:0
  • 點閱點閱:327
  • 評分評分:
  • 下載下載:33
  • 收藏至我的研究室書目清單書目收藏:0
本論文對於利用運算轉導放大器與接地電容(OTA-C)所製作的電壓模式、電流模式的多重回授迴路濾波電路,提出一套結構化、規則化的分析設計法則。目的在於期盼利用此一結構化的設計方法,實現任意階次的電壓模式或電流模式濾波電路,以使濾波電路的設計朝向系統化邁進。靈敏度的分析亦在本論文中加以探討,依據靈敏度的計算分析結果,研討OTA-C濾波電路在頻域領域上的可測試性(Testability),以介紹類比電路錯誤偵測時,可觀察性(Observability)的觀念,進而針對OTA-C濾波電路提出一些適當的測試頻率範圍與測試點,以增加電路錯誤的可觀察性。對於多階層的OTA-C濾波電路,本論文亦提出一套有效的測試方法,以改進多階層OTA-C濾波電路內部信號的可控制性(Controllability)與可觀察性。另一方面,一套以OTA-C 為基礎的內建自我測試(BIST)架構亦在本論文中提出,此一內建自我測試系統乃是針對類比電路的錯誤偵測而設計的,它不但可以增加測試的節點,亦可同時控制所有測試點的電壓訊號、降低錯誤觀察的時間,並且具有自我測試的能力。測試電路的佈線圖、實驗的測量值、OTA-C濾波電路的模擬結果,都在本論文的最後提出,以驗證理論探討的可行性與正確性。
Abstract
This thesis addresses the structural generation, analysis and synthesis of multiple loop feedback voltage-mode and current-mode operational transconductance amplifier and grounded capacitor (OTA-C, Gm-C) filters. A number of arbitrary order architectures including canonical realizations are developed. A general method for sensitivity analysis of the structures is also formulated. According to the sensitivity approach, we study the testability of OTA-C filters in the frequency domain by introducing the analog fault observability concept. The proposed methodology indicates the set of adequate test frequencies and test nodes to increase fault observability. A design for testability (DFT) approach to improve the controllability and observability of internal signals in the multi-stage OTA-C filters is also presented. The proposed DFT approach is effective in detecting single and multiple faults. Finally, a novel built-in self-test (BIST) structure based on OTA-Cs for the fault diagnosis of analog circuits is proposed. The proposed analog BIST structure can be used to increase the number of test points, sampling and controlling of all test points with voltage data, and making less time for test signal observable. The physical layouts, simulation results and experimental measurements are also presented to confirm the theoretical analysis.
COVER
CONTENTS
Chapter 1 Introduction
Chapter 2 Structural Design of OTA-C (Gm-C) Filters
2.1 Voltage-Mode Gm-C Filters
2.1.1 Basic Building Blocks
2.1.2 The Gm-C Filter Model
2.1.3 Feedback Coefficient Matrix
2.1.4 Synthesis Matrix
2.1.5 Structural Design Methodology
2.1.6 Second-Order Gm-C Filters
2.1.7 Third-Order Gm-C Filters
2.1.8 Nth-Order Gm-C Filters
2.2 Current-Mode OTA-C Filters
2.2.1 The MO-OTA-C Filter Model
2.2.2 System Equations and Transfer Functions
2.2.3 Feedback Matrix and Filter Structures
2.2.4 First-Order MO-OTA-C Filters
2.2.5 Second-Order MO-OTA-C Filters
2.2.6 Third-Order MO-OTA-C Filters
2.2.7 General Mth-Order MO-OTA-C Filters
Chapter 3 Testability Analysis and Testing Approach Based on OTA-C
3.1 Fault Observability of Gm-C Filters
3.1.1 General Sensitivity Reasoning
3.1.2 Ovservability Analysis
3.2 Testable Design of OTA-C Filters
3.2.1 Fault Modeling
3.2.2 Fundamental Theory
3.2.3 The DFT approach
3.2.4 The Circuit Under Test
3.2.5 Overhead Analysis
3.2.6 Physical Layout
3.3 OTA-C BIST Structure for Analog Circuits
3.3.1 The Self-Test Mode
3.3.2 The Built-in Test Mode
3.3.3 Timing Diagram
Chapter 4 Simulation and Measured Results
4.1 Third-Order Butterworth Gm-C Filter
4.2 Current-Mode MO-OTA-C Filters
4.3 Fault Observability of Gm-C Filter
4.4 Testable Third-Order IFLF Butterworth Gm-C Filter
4.4.1 Stuck-Short Fault
4.4.2 Deviation and Stuck-Open Fault
4.5 Experimental Results of BIST Structure
Chapter 5 Conclusions
Bibliography
Publication List
Bibliography
[1] R.L.Geiger and E.Sanchez-Sinencio, “Active filter design using operational transconductance amplifiers: A tutorial”, IEEE Circuit Devices Mag., pp. 20-32, 1985.
[2] R.L.Hiser and R.L. Geiger, “Impact of OTA nonlinearities on the performance of continue-time OTA-C bandpass filters”, IEEE Trans. Circuits Syst., Vol. 2, pp. 1167-1170, 1990.
[3] Y.Sun and J.K.Fidler, “Novel OTA-C realizations of biquadratic transfer functions”, Int. J. Electron., Vol. 75, pp. 333-340, 1993.
[4] Y.Sun and J.K.Fidler, “Resonator-based universal OTA-grounded capacitor filters”, Int. J. Circuit Theory Appl., Vol. 23, pp. 261-265, 1995.
[5] T.Tsukutani, M.Ishida, S. Tsuiki and Y. Fukui, “Versatile current-mode biquad filter using multiple current output OTAs”, Int. J. Electron., Vol. 80, No. 4, pp. 533-541, 1996.
[6] W.W.Guo, J.Y.Liu and S.Yang, “The realization of high-order OTA-C filter”, Int. J. Electron., Vol. 65, pp. 1153-1157, 1988.
[7] Y.Sun and J.K.Fidler, “OTA-C realization of general high-order transfer functions”, Electron. Lett., Vol. 29, pp. 1057-1058, 1993.
[8] J.Wu, “Current-mode high-order OTA-C filters”, Int. J. Electronics, Vol. 76, No. 6, pp. 1115-1120, 1994.
[9] R.Nawrocki, “Electronically controlled OTA-C filters with follow the leader feedback structure”, Int. J. Circuit Theory Appl., Vol. 16, pp. 93-96, 1988.
[10] Y.Sun, and J.K.Fidler, “Current-mode multiple-loop feedback filters using dual-output OTAs and grounded capacitors”, Int. J. Circuit Theory Appl., Vol. 25, pp. 69-80, 1997.
[11] Y.Sun, and J.K.Fidler, “Synthesis and performance analysis of universal minimum component integrator-based IFLF OTA-grounded capacitor filters”, IEE Proc. Circ. Devices Syst., Vol. 143, No. 2, pp. 107-114, 1996.
[12] Y.Sun, and J.K.Fidler, “Structure Generation Design of Multiple Loop Feedback OTA-Grounded Capacitor Filters”, IEEE Trans. Circuits Syst., Vol. 44, No. 1, pp. 1-11, 1997.
[13] G.Russell, and D.Learmouth, “Testing analogue functions using M-sequence”, Electron. Lett., Vol. 29, pp. 1818-1819, 1993.
[14] C.Y.Chao, H.J.Lin and L.Milor, “Optimal testing of VLSI analog circuit”, IEEE Trans. on Computer-Aided Design., Vol. 16, No. 1, pp. 58-77, 1997.
[15] M.Soma, “A design-for-test methodology for active analog filters”, IEEE Int. Test Conf., pp. 183-192, 1990.
[16] A.J.Bishop and A.Ivanov, “Fault simulation and testing of an OTA biquadratic filter”, IEEE Int. Test Conf., pp. 1764-17679, 1995.
[17] A.Milne, D.Taylor and K.Naylor, “Assessing and comparing fault coverage when testing analogue circuits”, IEE Proc. Circ. Devices Syst., Vol. 144, No. 1, pp. 1-4, 1997.
[18] M.Slamani and B.Kaminska, “Analog circuit fault diagnosis based on sensitivity computation and functional testing”, IEEE Design & Test Comput., pp. 30-39, 1992.
[19] M.Slamani and B.Kaminska, “Fault observability analysis of analog circuits in frequency domain”, IEEE Trans. Circuits Syst., Vol. 43, No. 2, pp. 134-139, 1996.
[20] C.L.Wey, “Built-in Self Test (BIST) structure for analog circuit fault diagnosis”, IEEE Trans. Instru. Meas. Vol. 39, No. 3, pp. 517-521, June 1990.
[21] C.L.Wey and S.Krishnan, “Built-in Self Test (BIST) structure for analog circuit fault diagnosis with current test data”, IEEE Trans. Instru. Meas., Vol. 41, No. 4, pp. 535-539, 1992.
[22] A.A. Hatzopoulos, S.Siskos, and J.M.Kontoleon, “A Complete Scheme of Built-in Self-test (BIST) Structure for Fault Diagnosis in Analog Circuits and Systems”, IEEE Trans. Instru. Meas., Vol. 42, No. 3, pp. 689-694, June 1993.
[23] L.T.Wurtz, “Built-in Self-test Structure for Mix-Mode Circuits”, IEEE Trans. Instru. Meas., Vol. 42, No. 1, pp. 25-29, 1993.
[24] Y.R.Shieh and C.W.Wu, “Control and Observation Structures for Analog Circuits”, IEEE Design & Test Comput., pp. 56-64, April 1998.
[25] C.M.Chang, C.C.Chien and H.Y.Wang, “Universal active current filters using single second-generation current conveyor”, Electron. Lett., Vol. 29, pp. 1159-1160, 1993.
[26] J.Ramirez-Angulo and E.Sanchez-Sinencio, “High Frequency compensated current-mode ladder filters using multiple output OTAs”, IEEE Trans. Circuits Syst. Ⅱ: Analog Digit. Signal Process., Vol. 49, No. 9, pp. 581-586, 1994.
[27] B.M.Al-Hashimi, “Current mode filter structure based on dual output transconductance amplifiers”, Electron. Lett., Vol. 32, No. 1, pp. 25-26, 1996.
[28] B.M.Al-Hashimi, “Systematic generation of current mode dual output OTA filters using a building block approach”, Int. J. Electron., Vol. 83, No. 1, pp. 37-48, 1997.
[29] B.M.Al-Hashimi, F.Dudek, M.Moniri, and J.Living, “Integrated universal biquad based on triple-output OTAs and using digitally programmable zeros”, IEE Proc. Circ. Devices Syst., Vol. 145, No. 3, pp. 192-196, June 1998.
[30] M.Tan and R.Schaumann, “Simulating general LC-ladder filters for monolithic realizations with only transconductance elements and grounded capacitors”, IEEE Trans. Circuits Syst., Vol. 36, No. 2, pp. 299-307, 1989.
[31] S.Szczepanski, A.Wyszynski and R.Cchaumann, “Highly linear voltage controlled CMOS transconductors”, IEEE Trans. Circuits Syst., Vol. 40, No. 4, pp. 258-262, 1993.
[32] J.Ramirez-Angulo, M.Robinson and E.Sanchez-Sinencio, “Current-mode continuous-time filters: two design approachs”, IEEE Trans. Circuits Syst. Ⅱ: Analog Digit. Signal Process., Vol. 39, No. 6, pp. 337-341, 1992.
[33] M.Slamani and B.Kaminska, “Analog circuit fault diagnosis based on sensitivity computation and functional testing”, IEEE Design & Test Comput., pp. 30-39, 1992.
[34] L.Milor and V.Visvanathan, “Detection of Catastrophic Faults in Analog Integrated Circuits”, IEEE Trans. Computer-Aided Design, Vol. 8, No. 2, pp. 114-130, February 1989.
[35] K.L.Lee, K.S.Huang and W.C.Wang, “Concurrent test method for OTA-C filters”, Electron. Lett., Vol. 33, No.1, pp. 1-2, January 1997.
[36] M.Soma, “Fault Coverage of CD Parametric Tests for Embedded Analog Amplifiers”, Proc. Int. Test Conf., pp. 566-571, 1993.
[37] G.Devarayanadurg and M.Soma, “Analytical Fault Modeling and Static Test Generation for Analog ICs”, Proc. Int. Conf. Computer-Aided Design, San Jose California, November 1994.
[38] A.J.Bishop and A.Ivanov, “On the Testability of CMOS Feedback Amplifiers”, IEEE Workssop on Detect and Fault Tolerance., Mtl, October 1994.
[39] K.R.Lakshmikumar, R.A.Hadaway and M.A.Copel, “Characterization and modeling of mismatch in MOS transistors for precision analog design”, IEEE J. Solid-State Circuits., Vol. SC-21, pp. 1057-1066, December 1986.
[40] J.Segura, A.Rubio and J.Figueras, “Analysis and modeling of MOS devices with hate oxide short failures”, Proc. Int. Symp. Circuits and Syst., pp. 2164-2167, 1991.
[41] M.F.Alshaibi and C.R.Kime, “A BIST Method for Random Pattern Resistant Circuits”, Int. Test Conf., pp. 176-185, 1996.
[42] E.J.McCluskey, “Built-in self-test technique”, IEEE Design Test Comput., vol. 2, pp. 21-28, April 1985.
[43] A.Chatterjee, “Concurrent Error Detection and Fault-Tolerance in Linear Analog Circuit Using Continuous Checksums”, IEEE Trans. VLSI Syst., Vol. 1, No. 2, pp. 138-149, June 1993.
[44] Y.R.Shieh and C.W.Wu, “Control and Observation Structures for Analog Circuits”, IEEE Design & Test Comp., pp. 56-64, April~June1998.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top