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研究生:鄭經華
研究生(外文):Ching-Hwa Cheng
論文名稱:CMOS骨牌電路的電荷分享效應分析、緩解與錯誤偵測
論文名稱(外文):Charge Sharing Effect Analysis, Alleviation and Fault Detection for CMOS Domino Circuits
指導教授:鍾文邦張世杰張世杰引用關係
指導教授(外文):Wen-Ben JoneShih-Chieh chang
學位類別:博士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2000
畢業學年度:89
語文別:中文
中文關鍵詞:骨牌電路電荷分享錯誤偵測緩解
外文關鍵詞:domino logic circuitcharge sharingfault detectionAlleviation
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因為動態CMOS電路提供較靜態CMOS電路更快的工作速度同時又具有較小的面積,所以常用於設計現代的高速電路(如CPU)。動態CMOS電路中又以骨牌(domino)電路的應用最廣。雖然動態的CMOS domino電路較靜態的 CMOS電路工作快速,然而 CMOS domino 電路卻需多考慮處理有關雜訊的問題,其中電荷分享(charge sharing--CS)是雜訊問題中最需特別考量的。Domino gate的電荷分享的問題之發生是由於事先 pre-charged 電荷被分佈於電路的內部節點的電容所分享後而產生的,因而造成輸出電位降低或更甚而造成錯誤的輸出值。在此論文中,我們將分析domino電路中電荷分享的情況,並仔細探討電路的拓樸圖及電路的 function與電荷分享的關係。我們建議一個來衡量每個 domino gate電荷分享程度的標準稱為CS-vulnerability。同時我們也提出計算每一個domino gate的 CS-vulnerability 的方法並導出其所對應的測試向量。另外,我們發展一個對輸入pin重新排列的方法用來減低每個domino gate的 CS-vulnerability,這個方式將可緩解電荷分享的程度。經分析,每個gate電荷分享的worst case至少需要兩個test pattern才能夠測到,測試pattern的得到可應用我們提供的pseudo gate法來產生。有關於多重 fault 的測試問題,傳統的 multiple stuck-at faults 需要很多的測試向量。我們證明對電荷分享錯誤只要利用單一電荷分享(single CS fault)之測試向量,便足以偵測所有的多重的電荷分享(multiple CS fault)錯誤。這個好的特性將能夠保證 domino 電路的電荷分享錯誤的測試品質。我們也發現傳統的scan測試方法無法正確的偵測電荷分享錯誤,因為scan的方式使得邊界(border)gate的CS錯誤無法查出,也就是missing error(誤放),原因是由提早準備好的test pattern所造成的。另外scan的低速測試的方式,也使得電路中正常的domino gate 因evaluation的時間過長而產生CS錯誤,也就是killing error(誤宰)。為此我們利用出二個DFT (Design-for-Testability)電路用來有效解決這兩種的測試錯誤。

Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design high-performance processors. However, domino logic suffers from several design problems and one of the most notable ones is the charge-sharing problem. Charge sharing which occurs in any CMOS domino gate may degrade the output voltage level or may even cause an erroneous output value. In this thesis, this problem is thoroughly investigated by considering circuit topology and circuit function. We describe a method to measure the sensitivity (called CS-vulnerability) of the charge-sharing (CS) problem for each domino gate. A method to derive the CS-vulnerability and the test vector for each domino gate is suggested. We also propose a transistor reordering method to dramatically reduce the CS-vulnerabilities for all domino gates, so that the CS problem can be alleviated. We also prove theoretically that a set of test vectors generated for single CS faults can also detect all multiple CS faults. This good property significantly guarantees the test quality for the CS faults of domino circuits. In this work, we also find that charge-sharing faults are extremely resistant to scan test. In fact, charge-sharing faults occurring at the border gates cannot be detected by any scan method, due to the missing error caused by early signal arrival time. Further, we show that killing error might happen in charge-sharing fault detection for both border gates and non-border gates because of the low-speed testing problem caused again by scan test. We thoroughly investigate both test errors and propose two design-for-testability techniques to efficiently eliminate both problems. To detect the worst-case charge-sharing faults, a two-pattern test technique is proposed, and the process of two-pattern test generation is also presented.

Contents
Abstract
1. Introduction1
2. Charge Sharing and CS-vulnerability8
2.1 The Cleaning Stage………………………………………9
2.2 The Cleaning Stage………………………………………12
3. Minimization of CS-vulnerability by Transistor Reordering 17
3.1 The CS-vulnerability of a Domino Gate…………………16
3.2 A Prune-and-Search Algorithm for Optimization Solution18
3.3 A Probability-Based Heuristic for Transistors Reordering21
3.4 Timing Considering………………………………….…..23
4. Fault Model and Test Generation25
4.1 Single CS Fault…………………………………………..27
4.2 Multiple CS Faults……………………………………….27
4.3 Derivation of Maximum of CS-transistors……………….32
4.4 Pseudo Gates and ATPG…………………………………34
4.5 Fault Simulation and Test Reduction…………………….35
4.6 Scan Design for Domino Circuits………………………..38
5. CS Test Errors in Scan Environment41
5.1 Missing Error of CS Fault Detection on Border Gates…...42
5.2 Killing Error of CS Faults Detection……………………..45
6. Design for Testability for Scan Test Errors47
6.1 The BDFT Circuit for Missing Error……………………….47
6.2 The CKDFT Circuit for Killing Error………………………49
7. CS Test Integration for Scan Design52
7.1 Test Application…………………………………………….52
7.2 Circuit Simulation…………………………………………..53
8. Experimental Results59
9. Conclusion84
10. Future Researches87
References89

[1] K. Bernstein, J. Ellis-Monaghan, and E. Nowak, “ High-Speed Design Styles Leverage IBM Technology Prowess,” IBM Micro News, Vol. 4, Number 3, 1998.
[2] F. Brglez, “On Testability of Combinational Networks,” Proc. of International Symposium on Circuits and Systems, pp. 221-225, 1984.
[3] P. E. Gronowski, W. J. Bowhill, D. R. Donchin, R. P. Blake-Campos, D. A. Cralson, E. R. Equi, B. J. Loughlin, S. Mehta, R. O. Muller, A. Olesin, D. J. W. Noorlag, R. P. Preston, “A 433-MHz 64-b Quad-Issue RISC Microprocessor,” IEEE Transcation on Solid-State Circuits, Vol. 31, pp. 1687-1695, Nov. 1996.
[4] P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K Gowan and R. L. Allmon, “High-Performance Microprocessor Design,” IEEE Transication on Solid-State Circuits, Vol. 33, pp. 676-686, May 1998.
[5] W. B. Jone, P. H. Madden, “Multiple Fault Testing Using Minimal Single Fault Test Set for Fanout-Free Circuits,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp. 149-157, Jan. 1993.
[6] S. M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill Book Co., 1996.
[7] K. J. Lee, M. A. Breuer, “On the Charging Sharing Problem in CMOS Stuck-Open Fault Testing”, Proc. International Test Conference, pp. 417-426, 1990.
[8] R. Puri, A. Bjorksten, T. E. Rosser, “Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis,” Proc. IEEE International Conference on Computer-Aidded Design, pp. 2-8, 1996.
[9] M. R. Prasad, D. Kirkpatrick, R. K. Brayton, A. L. Sangiovanni-Vincentelli, “Domino Logic Synthesis and Technology Mapping,” Proc. IEEE/ACM International Workshop on Logic Synthesis, 1997.
[10] J. A. Pretorius, A. S. Shubat, C. A. Salama, “Charge Redistribution and Noise Margins in Domino CMOS logic,” IEEE Transactions on Circuits and Systems, Vol. CAS-33, pp. 786-793, Aug. 1986.
[11] S. C. Prasad, K. Roy, “Transistor Reordering for Power Minimization Under Delay Constraint,” ACM Transaction on Design Automation of Electronic Systems, Vol. 1, No. 2, pp. 280-300, April 1996.
[12] P. Srivastava, A. Pua, L. Weich, “Issues in the Design of Domino Logic Circuits,” Proc. IEEE Great Lakes Symposium on VLSI, pp. 109-113, 1998.
[13] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Muragi, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, “SIS: A System for Sequential Synthesis,” U. C. Berkeley, Technical Report UCB/ERL M92/41, May 1992.
[14] N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design-A Systems Perspective, 2nd Edition, Addison-Wesley Pub. Co., 1992.
[15] Z. Wang, G. A. Jullien, W. C. Miller, J. Wang, S. S. Bizzan, “Fast Adder Using Enhanced Multiple-Output Domino Logic,” IEEE Transaction on Solid-State Circuits, Vol. 32, pp. 206-214, Feb. 1997.
[16] S. C. Chang, W. B. Jone and S. S. Chang, “TAIR: Testability Analysis by Implication Reasoning,” IEEE Transaction on Computer Aided Design, Vol. 19, pp152-160, Jan. 2000.
[17] Taiwan Semiconductor Manufacture Corporation, 0.35μm CMOS ASIC process Digests, 1999.
[18] Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, and Shih-Chieh Chang, “ Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000.
[19] C. H. Cheng, S. C. Chang, J. S. Wang, W. B. Jone, “Charge Sharing Detection for CMOS Domino Logic Circuit,” Proc. IEEE International Symposium On Defect and Fault Tolerance in VLSI System, pp. 77-85, 1999.
[20] D. Heidel, A. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz, “High Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor,” Proc. IEEE International Test Conference, pp. 234-238, 1998.
[21] A. Krstic, K. T. Cheng, S. T. Chakradhar, “Testing High Speed VLSI Devices Using Slower Testers,” Proc. of IEEE VLSI Test Symposium, pp. 16-21, April 1999.
[22] N. K. Jha, Q. Tong, “Testing in Multiple-Output Domino Logic (MODL) CMOS circuits,” IEEE Trans. on Solid-State Circuits, Vol. 25, No. 3, June 1990, pp.800-805.
[23] Oklobdzija, Kovijanic, ”On testability of CMOS-domino logic,” Int. Conf. on Fault Tolerant Computer, pp. 50-55, 1984.
[24] Figueras, Renovell, “ Current Testing in Dynamic CMOS Circuits,” Journal of electronic testing: Theory and Applications, Vol. 6, pp. 127-131, 1995.
[25] N.K. Jha, Q. Tong, “Testing of Multiple-Output Domino Logic,” IEEE trans. on CAD, pp. 1-4, 1990.
[26] V. D. Agrawal, T. J. Chakraborty, “High-Performance Circuit Testing with Slow-Speed Testers,” Proc .IEEE International Test Conference, pp. 302-310, 1995.
[27] M. R. Prasad, D. Kirkpatrick, R. K. Brayton, A. L. Sangiovanni-Vincentelli, “Domino Logic Synthesis and Technology Mapping,” Proc. IEEE/ACM International Workshop on Logic Synthesis, 1997.

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