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研究生:劉奇昌
研究生(外文):Chi-Chang Liu
論文名稱:高效能RSA密碼系統之硬體設計
論文名稱(外文):Hardware Implementation of High Performance RSA Cryptosystem
指導教授:張雲南張雲南引用關係
指導教授(外文):Yun-Nan Chang
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:45
中文關鍵詞:RSA密碼學Montgomery模數乘法
外文關鍵詞:RSAMontgomerymodular multiplication
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隨著網際網路的快速發展和愈加多元的廣泛應用,資訊安全的問題也愈來愈重要。而RSA公開金匙密碼學則是目前漸漸被廣泛使用的一種保護重要資料的方法。
本論文中,提出一種以Montgomery modular multiplication algorithm為基礎的RSA公開金匙密碼學的硬體架構。除了繼承Montgomery algorithm單純使用加法和移位就能計算A×B (mod N),並加以改良成每個時脈以兩個位數為基本運算的單位,成功地將原本的演算法中,所需要的迴圈重複次數,減為原來的一半,加快其運算的速度,而且所需要的硬體成本也相當低,是兼具效能和成本的設計方式。
With the explosively growing number of various network applications, information security issue of the network has received more and more attention. RSA algorithm is one of the most popular and reliable methodologies that have been widely used today to provide secure data transmission. In this thesis, a novel VLSI architecture of RSA public key cryptosystem based on radix-4 Montgomery modular multiplication is proposed. By using the Booth encoding with the modified Montgomery algorithm, a high performance Montgomery multiplier has been designed such that the iteration of computation required can be reduced by a half while the cost of additional hardware is minimized. In addition, both squaring and multiplication operations of the intermediate result are implemented in the same module alternatively. Therefore, the resulted architecture cannot only achieve highly hardware utilization but also deliver high throughput of RSA computation.
中文摘要………………………………………………………………….i
英文摘要…………………………………………………………………ii
目錄……………………………………………………………………...iii
圖片列表………………………………………………………….……...v
表格列表…………………………………………………………...……vi
第一章緒論
1.1 研究背景..………………………………………..……………..1
1.2 研究動機..………………………………………………..……..1
1.3 論文架構..……………………………………………..………..2
第二章密碼系統
2.1 概論..…………………………………………………..……….3
2.2 傳統密碼學..………………………………………….…….….5
2.3 公開金匙密碼學..…………………………………….….…….6
2.4 RSA公開金匙密碼學..……………………………….…..……7
第三章RSA的相關設計
3.1 架構的分類..……………………………………………..…...10
3.2 Montgomery algorithm.……………………………...………12
3.2.1 由來..……………………………………………………12
3.2.2 運作原理..………………………………………………13
3.2.3 優點和缺點..……………………………………………14
3.3 Montgomery algorithm的相關研究..…………………...…..15
第四章設計原理和硬體架構
4.1 設計原理及演算法………………………………………..….19
4.2 處理器整體的硬體設計………………………………..…….25
4.3 Booth Serial Multiplier…………………………………....….27
4.4 Montgomery Module…………………………………………31
4.5 Carry Propagation Adder……………………………………35
4.6 結果和效能分析…………………………………...…………36
第五章結論與未來的研究方向..……………………………….…….42
參考文獻..……………………………………………………….…...…43
參考文獻
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