(3.92.96.236) 您好！臺灣時間：2021/05/09 00:47

### 詳目顯示:::

:

• 被引用:0
• 點閱:116
• 評分:
• 下載:0
• 書目收藏:0
 邏輯合成的目的在於將電路由原先的設計轉換成一個以邏輯閘架構而成的邏輯電路設計。其轉換的過程，考量著電路的各式設計需求，如電路的速度、面積以及電路的省電效率。目前在邏輯合成步驟中，已經有許多用來提高電路速度的最佳化演算法。其中有一些演算法經由改變電路的結構來達到提升電路速度的目的。傳統上，這些以提升電路速度為目的的電路結構重整大多針對在邏輯方程式上。其主要的缺點是速度延遲的計算在邏輯方程式的階段通常並不十分正確。這可能使電路最佳化的效果大打折扣。此外，電路的結構對電路的整體延遲有著顯著的影響。維持一個好的電路結構對於電路速度的最佳化相當重要。在本篇論文中，我們的目的在使用電路結構重整來實行一個電路速度的最佳化。有一種以換線技巧我們稱為Global flow optimization。它可以將邏輯閘的輸出輸入訊號線用另外一組輸出輸入訊號線替換。本論文中，我們將採用了global flow optimization的框架。為了將global flow optimization使用在提升電路速度上，我們需要修改於先的程序並且產生新的機制來找到可以用來提升電路速度的電路重新連結的方式。
 The purpose of logic synthesis is to derive a gate level implementation from the initial specification taking into account several design objectives in mind such as timing, area and power. There have been many timing optimization algorithms proposed previously in the logic synthesis step. Some techniques perform timing optimization by modify the circuit structure. Traditionally, techniques of timing driven logic restructuring perform on the logic equations. The major draw back is that the delay estimation in the logic equation step cannot be accurate. It may lead to sub-optimal results. On the other hand, it was known that the structure of a circuit might have significant impacts on the delay results. Obtaining good structure is important for timing optimization. In this thesis, our objective is to perform logic restructuring for timing improvement. There is a (logical) wire replacement technique called Global Flow Optimization (GFO) which attempts replace fanins/fanouts of a node by a new set of fanins/fanouts. Our idea is to adopt the framework of the GFO. In order to turn for timing driven optimization, we need to modify the original routine in the GFO and develop a mechanism to find proper reconnection solutions.
 中文摘要1 Abstract2 Chapter 1 Introduction3 Chapter 2 The Global Flow Optimization6 Chapter 3 Timing Restructuring GFO11 Chapter 4 Experimental Results17 Chapter 5 Conclusions19 Reference21
 1 ] C. L. Berman and L. H. Trevillyan. “Global Flow Optimization in Automatic Logic Design,” IEEE Trans. CAD 10, pp. 557-564, May 1991.[ 2 ] Chen-Liang Fang and Wen-Ben Jone. ”Timing optimization by gate resizing and critical path identification,” IEEE Transactions. Computer-Aided Design of Integrated Circuits and Systems volume 14, pp. 201 —217,Feb. 1995.[ 3 ] Nishio, S and Kitahara, T. “Incremental timing optimization during multiple stages of logic synthesis,” Proc of Fourth Annual IEEE Internationa,l ASIC Conference and Exhibit, pp. P13 -1/1-4, 1991.[ 4 ] Kwang-Ting Cheng and Entrena, L.A. “Multi-level logic optimization by redundancy addition and removal,” Proceedings [4th] European Conference, Design Automation with the European Event in ASIC Design, pp. 373 —377, Feb 1993.[ 5 ] Wei Chen and Cheng-Ta Hsieh. “Simultaneous gate sizing and fanout optimization,” ICCAD-2000, IEEE/ACM International Conference on 2000, Computer Aided Design, pp. 374 —378, 2000.[ 6 ] Chun-Hong Chen and Chi-Ying Tsui. “Timing optimization of logic network using gate duplication,” Proc of the ASP-DAC '99 Asia and South Pacific 1999, Design Automation Conference, vol.1, pp. 233 —236, 1999.[ 7 ] Kung, D.S. “A fast fanout optimization algorithm for near-continuous buffer libraries,” Proc of Design Automation Conference, pp. 352 —355, 1998.[ 8 ] Chun-Hong Chen and Chi-Ying Tsui, “Timing optimization of logic network using gate duplication,” Design Automation Conference, Proc of the ASP-DAC '99. Asia and South Pacific, vol.1, pp.233 —236, 1999.[ 9 ] Aggarwal, R and Murgai, R. “Speeding up technology-independent timing optimization by network partitioning,” IEEE/ACM International Conference, Computer-Aided Design, Digest of Technical Papers 1997, pp. 83 —90, 1997.[ 10 ] Paulin, P.G. and Poirot, F.J. “Logic decomposition algorithms for the timing optimization of multi-level logic" IEEE International Conference, Computer Design, Proc of VLSI in Computers and Processors, pp. 329 —333, 1998.[ 11 ] Damiano, R. and Berman, L. “Dual global flow,” 1991. ICCD '91. Proc of IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 49 —53.
 推文當script無法執行時可按︰推文 網路書籤當script無法執行時可按︰網路書籤 推薦當script無法執行時可按︰推薦 評分當script無法執行時可按︰評分 引用網址當script無法執行時可按︰引用網址 轉寄當script無法執行時可按︰轉寄

 無相關論文

 1 8.馬孝璿，民88，兩稅合一對上市上櫃公司股利政策影響之探討，財稅研究第三十一卷第六期，頁134-158。 2 15.林峻民，民88年3月，兩稅合一制度下參與除權之租稅效果評估，大信投資季刊，pp.54-58。 3 16.許崇源，民89，兩稅合一制對我國營利事業所得稅會計處理及投資人財務報表使用之影響，會計研究月刊第172期，pp.49-59。 4 游能悌，鄧屬予，1996，台灣北部中上中新統的岩相與沈積循環，地質 第15卷 第二期，第29-60頁。 5 游能悌，鄧屬予，1999，台灣北部大寮層與石底層之沈積環境，經濟部中央地質調查所彙刊 第十二號，第99-131頁。 6 蔡龍珆，1988，基隆－台北間煤層鏡煤素之共生次序含意，地質第8卷，1-2期，63-70頁。

 1 網頁資源資訊擷取 2 投票系統及其應用 3 物件化網格產生之三角形群組問題 4 物件化網格產生之初使網格最佳化 5 最大葉節點生成樹的改善近似演算法 6 個人化資訊訂閱與搜尋 7 減輕動態可邏輯化陣列CrossTalk的情況 8 應用全域流量最佳化的方法作佈局後繞線長度之最小化 9 在Virtuoso上雷達平行處理之實作 10 運用在多埠式嵌入式記憶體中的平行測試方法 11 全球網路資源抓取 12 以機率為基礎在異質網路下多重群播排程之最佳化 13 異質叢集系統中廣播及合併排程之最佳化 14 移動式物件在關連式資料庫中的管理與漸近式查詢 15 應用於三十二位元微處理器之可測試設計及實踐

 簡易查詢 | 進階查詢 | 熱門排行 | 我的研究室