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研究生:陳政雄
研究生(外文):Zheng-Xiong Chen
論文名稱:利用VLSI設計一低複雜度的RS編/解碼架構
論文名稱(外文):A low-complexity VLSI architecture of the Reed-Solomon codec
指導教授:陳自強陳自強引用關係
指導教授(外文):Oscal T.-C. Chen
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:58
中文關鍵詞:RS碼
外文關鍵詞:Reed-Solomon code
相關次數:
  • 被引用被引用:6
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本論文的內容主要利用Reed-Solomon(RS) code的編解碼演算法原理,使其能應用在硬體設計上,並且將RS晶片設計成具有可變糾錯能力的功能,使此晶片的設計規格能符合Cable modem之DOCSIS所訂規格,並對不同雜訊的干擾而有不同的傳輸模式,所以此RS晶片將可以有效率的對編碼後的訊號做傳輸。而本RS晶片在解碼電路所用到的演算法有求錯誤位置多項式係數的Division-free Berlekamp-Massey algorithm、Chien search、求錯誤值的Forney algorithm以及利用修正後的Fermat’s theorem來實現有限場元素除法運算,使除法電路的複雜度可以降低。由於目前網路上的資料傳輸速度不需要達到很快的接收速度,而本晶片完成後的資料處理速度高出網路上的資料傳輸速度規格的要求太多,因此在不考慮速度的情況下,我們另外在論文最後面提出並設計一低成本RS晶片架構,其處理速度比較符合現今網路上資料的傳輸速度又能節省晶片的設計面積。希冀本論文最後提出之低成本RS解碼架構其處理速度能符合現今網路上資料的傳輸速度而不會造成晶片設計時面積的浪費。
In this dissertation, we explore the principle of the Reed-Solomon codec and design its VLSI architecture, which is suitable for specifications of the cable modem with programmable error-correction numbers and codeword lengths. The proposed RS codec processor includes an encoder and a decoder, especially in the decoder that consists of syndrome computation units, a division-free Berlekamp-Massey (DFBM) algorithm unit, an coefficient generation unit, a Chien search unit, and a Forney-algorithm unit. The modified Fermat’s theorem is utilized to reduce the complexity of the finite-field division. With consideration of the internet data transmission rate, the proposed RS codec processor can be further investigated by compromising throughput rates and hardware complexities. Hence, a low-complexity RS codec processor is designed to employ 2 syndrome computation units, a symbol-serial DFBM algorithm unit, a chien search unit and a symbol-serial Forney-algorithm unit. The RS codec processor proposed herein can be widely used in various communication systems such as wireless transmission, digital television, cable modem, and aeronautical telecommunication.
目錄
第一章Channel coding簡介 2
1.1 前言 2
1.2糾錯碼簡介 3
1.3 糾錯碼的類別及演進 4
1.4糾錯碼現今的發展概況 5
第二章Reed-Solomon碼原理 7
2.1 研究目的 7
2.2理論分析 8
2.3各種RS解碼架構探討 10
2.3.1 algebraic decoding 11
2.3.2 transform decoding 13
2.4求出錯誤位置多項式係數的演算法 16
2.4.1 Berlekamp-Massey演算法 17
2.4.2 Euclidean演算法 20
2.4.3 Division-free Berlekamp-Massey(BM)演算法 23
2.4.4 time domain BM algorithm 25
2.5 本RS decoder所採用的架構 27
2.5.1 Chien search 28
2.5.2 Forney演算法 28
第三章 有限場元素運算的電路實現 30
3.1有限場乘法器的電路架構 31
3.2有限場除法器的電路架構 37
第四章Reed-Solomon Codec架構設計 41
4.1 RS encoder architecture 42
4.2 RS decoder architecture 43
4.3晶片設計規格及架構比較 48
4.4 低成本的RS晶片設計 50
第五章 結論 55
參考文獻 57
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[20]Zheng-Xiong Chen, Nan-Ying Shen, Oscal T.-C. Chen, Yuh-Feng Hsu, Yuh-Jou Tsen, and Daniel Y. Perng, “A Programmable Reed-Solomon Codec Processor,” IEEE Midwest Symposium on Circuits and Systems, pp.359-362, August 2001.
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