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研究生:蔡博義
論文名稱:適用於纜線數據機之可程式化里德-所羅門碼解碼器製作
論文名稱(外文):A programmable Reed-Solomon decoder for cable modem
指導教授:袁正績魏學文魏學文引用關係
學位類別:碩士
校院名稱:中華大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:64
中文關鍵詞:里德-所羅門碼纜線數據機
外文關鍵詞:Reed-Solomon codecable modem
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Reed-Solomon碼是高速率數位通訊傳輸系統上廣泛被使用的一種錯誤更正碼,本論文利用Inverse-Free Berlekamp-Massey 演算法設計了一個適用於纜線數據機下行的Reed-Solomon碼可程式化解碼器,此解碼器所能更正的錯誤符元(symbol)個數最多可達10個,碼長度(code word length)可以在45~255個符元之間變動。
本論文所設計的解碼器,碼長和錯誤更正能力是可變的,若需要不同的碼長(n值)及錯誤更正能力(t值),電路不必重新設計,只需更動程式內容即可。且以此電路架構,設計應用於其他系統的Reed-Solomon碼解碼器,如果需要較大的錯誤更正能力t,電路只需要小幅修改,就可達成目的。
我們使用Xilinx公司所生產的FPGA chip,Virtex-E系列來施行電路製作,測試結果電路設計正確,符合纜線數據機之規格需求。

Reed-Solomon (RS) code is a powerful forward-error-correcting (FEC) code that has been widely used for high speed digital communication systems. In this thesis, based on inverse-free Berlekamp-Massey algorithm, we design a programmable RS decoder for cable-modem applications. The proposed RS decoder can correct up to 10 errors and the codeword length can vary from 45 to 255. The whole hardware circuits are finally simulated and verified by using a FPGA development system from Xilinx Company. Under a simple test-bed system, this proposed RS decoder is illustrated to fit the cable modem specification.

第一章 緒論............................................. 1
第二章 符合纜線數據機規格之Reed-Solomon編解碼方法研究... 5
2-1.Reed-Solomon解碼法介紹.............................. 5
2-1-1.RS碼介紹.......................................... 5
2-1-2. Inverse-Free Berlekamp-Massey algorithm.......... 10
2-2.纜線數據機之Reed-Solomon編解碼...................... 25
2-2-1.規格.............................................. 25
2-2-2.纜線數據機RS codes的解碼法........................ 28
第三章 Reed-Solomon解碼器電路設計....................... 32
第四章 電路實現與驗證................................... 53
第五章 結論............................................. 61
參考文獻................................................ 62
Appendix A.............................................. 64

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[10] “Data-Over-Cable Service Interface Specifications, Radio Frequency Interface Specification”, SP-RFI v1.1-I01-990311
[11] Hsie-Chia Chang and C. Bernard Shung,“New Serial Architecture for the Berlekamp-Massey Algotithm,”IEEE Trans. Communication, Vol. 47, No. 4, pp. 481-483, April 1999
[12] I. S .Reed and M. T. Shin and T. K. Truong“VLSI design of inverse-free Berlekamp-Massey algorithm,”IEE PROCEEDINGS-E, Vol. 138, No. 5, September 1991
[13] Jyh-Horng Jeng and Trieu-Kien Truong“On Decoding of Both Errors and Erasures of a Reed-Solomon Code Using an Inverse-Free Berlekamp-Massey Algorithm,”IEEE Trans. Communications, Vol. 47, No. 10, pp. 1488-1494, October 1999
[14] I. S. HSU and T. K. TRUONG and L. J. DEUTSCH and I. S. REED“A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases”IEEE Trans. Computers, Vol. 37, No. 6, pp. 735-739, June 1988
[15] HOWARD M. SHAO and IRVING S. REED“On the VLSI Design of a Pipeling Reed-Solomon Decoder Using Systolic Arrays”IEEE Trans. Computers, Vol. 37,No. 10, pp. 1273-1280, October 1988
[16] SHU LIN, DANIEL J. COSTELLO, Jr.“Error Control Coding - Fundamentals and Applications”Prentice-Hill, 1979
[17] 陳進益“纜線數據機錯誤更正碼研究、性能分析及軟體施行,”中華大學碩士論文

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