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研究生:紀俊呈
研究生(外文):Jun-Cheng Chi
論文名稱:超大型積體電路佈局之電力線繞線方法
論文名稱(外文):A Power and Ground Routing Methodology for VLSI Layout.
指導教授:陳美麗陳美麗引用關係
指導教授(外文):Mely Chen Chi
學位類別:碩士
校院名稱:中原大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:37
中文關鍵詞:電力線電力線繞線繞線流程整合電力線架構
外文關鍵詞:Power and ground routingRoutingPower and ground busesFlow integrationPower and ground topology
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電力線的繞線問題,在IC設計領域是個十分重要的問題。本文提出一個新的電力線繞線方法,在一個已經擺置完成的IC晶片上,使用兩層金屬層,繞上樹狀的電力線架構。在一個晶片上,可能會有許多的power/ground pad分佈在晶片的周圍,所以電力線的架構,可能會被建構成多棵樹狀的架構,以減少所消耗的繞線資源。
本電力線繞線方法應用修改過的Dijkstra的演算法,由pin到pad搜尋一條佔用最少繞線資源的路徑,繞線資源是繞線面積及因繞線所佔用的額外pitch面積的總和,因為這些保留的pitch空間,並不能用來繞其他的線路,所以使用繞線資源當cost function,比單獨使用wire的長度或面積的方式,更能準確的評估繞線的品質,實驗結果顯示,用wire area + pitch area當cost function,所佔用的繞線資源,比僅用wire area當cost function的繞線結果來的少。
而在繞這些電力線的時候,需根據電子移轉及電壓降的限制,計算出電力線的寬度,並需符合製程上的限制。本繞線器已用C語言實現,並已與商用CAD佈局工具的IC設計流程整合。實驗結果請參考第五章。

The power and ground routing problem is an important issue in VLSI circuit design. This paper proposes a new router which can be used to route power and ground nets through the use of double metal layers. It was developed for integrated circuit designs. A chip may have multiple power/ground pads located on any side of the chip. Multiple trees may be constructed for power or ground nets to consume as a smaller routing resource.
The routing algorithm used is a modification of Dijkstra’s algorithm, which searches for the shortest path between a pin and a pad. It uses a new metric for the cost function. The cost is the total area of routing wires and the adjacent pitch region due to the routing path. This new metric is more accurate in the measuring the quality of routing than wire length/area alone because the reserved pitch region may not be used for routing any other net. The experimental results shows that use the new cost function would consumes less routing resource than use the wire area as cost function.
The power and ground nets are routed under the constraints of electromigration and voltage drop of the chip. This router is integrated into an IC design flow of a commercial CAD layout tool. Experimental results are shown.

目 錄
中文摘要……………………………………………………………………………….I
Abstract……………………………………………………………………………….II
誌 謝…………………………………………………………………………………III
第一章導論………………………………………………………………………1
第二章問題描述與定義…………………………………………………………3
2.1 問題描述………………………………………….…………………….3
2.2 電壓降的限制…………………………………………………………..4
2.3 電子移轉的限制…………………………………………………….….5
2.4 Bisection Method 概述…………………………………………….5
2.5 製程的限制………………………………………………………….….7
2.6 名詞定義……………………………………………………………..…8
第三章流程及演算法………………………………………………………...10
3.1 演算法流程……………………………………………………….…10
3.1.1 讀入資料………..………………….………………….……….10
3.1.2 建立Routing Graph………..………………….…………….11
3.1.3 將power/ground pin 作排序………..……………...……….14
3.1.4 搜尋最小cost的路徑………..………………….…………….14
3.1.5 繞線………..………………….…………………………..…….20
3.2 流程圖及演算法………..………………….…………………………22
3.2.1 流程圖………..………………….………………………….…...22
3.2.1 演算法………..………………….……………………………....23
3.3 複雜度分析…….……..………………….…………………………24
第四章流程整合………..………………….……………………………..……26
4.1 與流程整合範例………..………………….…………………………27
第五章實驗結果………..………………….……………………….………....28
5.1 工作平台及程式語言………..………………….…………………....28
5.2 實驗結果………..………………….………………………………....28
第六章結論及未來研究方向………..………………….……………………..30
6.1 結論………..………………….……………………………………....30
6.2 未來研究方向………..………………….…………………………....30
參考資料………..………………….……………………………..…………………31
附錄:
A. 作者簡介……………………………………………...…………………..32

參考資料[1] Z. A. Syed and A. El Gamal, “Single layer routing of power and ground networks in integrated circuits”, Journal of Digital System, Vol.6, No.1, pp.53-56, 1982.[2] Xiao-Ming Xiong and E. S. Kuh, “The Scan Line Approach to Power and Ground Routing”, Proc. Of ICCAD, pp.6-9, 1986.[3] S. Haruyama and D. Fussell, “A New Area-Efficient Power Routing Algorithm for VLSI Layout,” Proc. of ICCAD, pp.38-41, 1987.[4] R. Dutta and M. Marek-Sadowska, “Automatic Sizing of Power/Ground (P/G) Networks in VLSI,” Proc. of 26th Design Automation Conference, pp.783-786,June 1989.[5] S. Chowdhury, “Optimum Design of Reliable IC Power Networks Having General Graph Technologies”, proc. of 26th DA Conference, pp.787-790, 1989.[6] T. Mitsu Hashi and E. S. Kuh, “Power and Ground Network Topology Optimization”, proc. of 29th DA Conf., pp.524-529,1992[7] X. Wu, C. Qiao, and X. Hong, “Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells”, proc. of 36th DA Conf., pp.21-24, 1999.[8] X. Tan, C. Shi, D. Lungeanu, J. C. Lee, and L. P. Yuan, “Reliability-Constrained Area Optimization of VLSI Power/Ground Network Via Sequence of Linear Programming”, proc. of 36th DA Conf., pp.78-82, 1999.[9] K. Erhard, F. Johannes, and R. Dachauer, “Topology Optimization Techniques for Power/Ground Networks in VLSI”, proc. of 29th DA Conf., pp.362-367, 1992[10] ApolloII User Guide, Avant! Crop., 1999[11] Menahem Friedman, Abraham Kandel, Fundamentals of Computer Numerical Analysis, CRC Press, Inc., Pages 116, 1994.[12] Sabih H. Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons Ltd, Pages 34, 1999.

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