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研究生:張獻文
研究生(外文):Hsien-Wen Chang
論文名稱:低功率導向之超大型積體電路分割與擺置方法
論文名稱(外文):VLSI Circuit Partitioning and Placement for Low Power Design
指導教授:陳美麗陳美麗引用關係
指導教授(外文):Mely Chen-Chi
學位類別:碩士
校院名稱:中原大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:46
中文關鍵詞:功率消耗切換頻率電路分割時鐘訊號線
外文關鍵詞:switching ratecircuit partitioningpower consumptionclock net
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在超大型積體電路設計的領域中,功率消耗是很重要的問題。本文中,我們使用四分法(Quadrisection)的方式以F-M分割為基礎,並利用[1]中所提之增益值更新(gain update)方法,對電路進行分割,接著再以重複分割的技巧來完成擺置。在分割與擺置的過程中我們針對導線負載(wire load)所產生的功率消耗進行最佳化,來降低整體功率消耗,並同時以各分割區塊間面積和邏輯閘負載(gate load)功率消耗的平衡作為分割時的限制條件,使功率消耗能平均分布。
在執行電路分割與擺置的過程中,我們使用了不同的cost function做比較,由實驗結果可以發現,若在cost function中加入功率消耗的因素(訊號切換頻率)作考量,可以有效降低整體的功率消耗。另外,在分割時的限制上,除了基本的平均面積外,我們再針對是否有平均gate load功率消耗作實驗,很明顯的在加了這樣的限制後,不但可以平均分散電路的gate load 功率消耗而且也能降低切換頻率較高的導線其擁擠程度。除此之外,在分割的過程中,我們還特別考量時鐘訊號線(clock net)將其加權處理,除了能降低clock net本身的功率消耗還能再降低整體的功率消耗。詳細實驗結果請參考第五章。

Power consumption is an important issue in VLSI circuit design. In this paper, we use quadrisection algorithm based on F-M partitioning, and the gain update scheme proposed in [1] to perform our partitioning process. Then, we use iterative partitioning to complete placement. In the partitioning and placement process, wire load power consumption is concerned to reduce total power, and gate load power consumption is added in the constraint to obtain uniform power distribution.
The experimental result shows that, concerning switching rate in the cost function computing can reduce total wire load power consumption. Except area constraint, if gate load power constraint is added, we can distribute gate load power consumption uniformly and reduce the conjunction of high switching rate nets. Further more, we also think of high switching and high fanout nets especially clock net. After the cost of clock is multiplied by a weight(>1), we can not only reduce the power of the clock net but also reduce the total power. Experimental results are shown.

中文摘要………………………………………………………………...I
Abstract…………………………………………………………………II
誌謝……………………………………………………………………III
第一章 前言…………………………………………………………1
第二章 分割與擺置問題……………………………………………3
2-1 電路分割問題…………………………………………………...3
2-2 最小切線量電路擺置方法……………………………………...4
第三章 問題描述與方法……………………………………………6
3-1 問題描述………………………………………………………...6
3-2 以分割為基礎的電路擺置方法………………………………...9
第四章 程式流程與演算法………………………………………..16
4-1 演算法流程…………………………………………………….16
4-2 整體演算法…………………………………………………….24
4-3 流程圖………………………………………………………….25
第五章 結果與實驗數據…………………………………………..26
5-1 工作平台及程式語言………………………………………….26
5-2 實驗數據與分析……………………………………………….26
第六章 結論與未來方向…………………………………………..39
6-1 結論…………………………………………………………….39
6-2 未來方向……………………………………………………….39
參考資料………………………………………………………………40

[1] Dennis J.-H. Huang and Andrew B. Kahng. “Partitioning-Based Standard-Cell Global Placement with an Exact Objective.” ISPD’ 97.[2] Hirendu Vaishnav and Massoud Pedram. “A Performance Driven Placement Algorithm for Low Power Designs.” Design Automation Conference, 1993.[3] Peter R. Suaris and Gershon Kedem. “Quadrisection: A New Approach to Standard Cell Layout.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987.[4] Synopsys Power Compiler Reference Manual.[5] Avant! Galax! Passport CB35DP152 0.35μm — 3.3Volt High - Density Datapath Library.[6] I.-S. Choi and S.-Y. Hwang. “Circuit partitioning algorithm for low-power design under area constraints using simulated annealing.” Circuits, Devices and Systems, IEE Proceedings-.[7] Lee, H.D., Lee, J.S., and Hwang, S.Y. “A novel high level synthesis algorithm for low power ASIC design.” J. Microelectronic System Integration, 1996, 4, (4), pp. 219-232.[8] Farid N. Najm. “Power Estimating Techniques for Integrated Circuits.” IEEE/ACM International Conference on Computer-Aided Design, 1995.[9] Subodh Gupta and Farid N. Najm. “Power Modeling for High-Level Power Estimation.” IEEE Transactions on VLSI Systems, VOL. 8, NO. 1, FEBRYARY 2000.[10] M. Huang, R. Kwok and S.-P. Chan. “Simplified and accurate power-analysis method for deep-submicron ASIC designs.” IEE Proc.-Circuits Devices Syst., Vol.147, No. 3, June 2000.[11] Fiduccia and Mattheyses. “A linear time heuristic for improving network partitions.” 19th Design Automation Conference, 1982.[12] B. W. Kernighan and S. Lin. “An Efficient Heuristic Procedure for Partitioning Graphs.” Bell Syst. Tech. J., 49(2): 291-307, 1970.[13] M. A. Breuer, “A Class of Min-Cut Placement Algorithm for the Placement of Standard Cells.” Proceedings of the ACM/IEEE Design Automation Conf., pp. 284-290, 1997.[14] www.cs.ucla.edu/~xjyang/Dragon/[15] A. Ghosh, S. Devadas, K. Kuetzer, and J. White. “Estimation of average switching activity in combinational and sequential circuits.” Proceedings of the 29th DAC, pages 370-375, June 1992.[16] Shih-Hsu Huang, Mely Chen-Chi, and Hsu-Ming Hsiao, “A Practical Interconnect-Driven Design Methodology for Low Power ASIC Designs.” Chung Yuan Journal, Vol. 29, No.1, March, 2001.

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