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研究生:巫昆霖
研究生(外文):Kun-Lin Wu
論文名稱:軟體定義無線電系統中數位中頻可程式化降頻器設計
論文名稱(外文):Development of Digital IF Programmable Downconverter for Software Defined Radio Transceiver
指導教授:鄭獻勳繆紹綱繆紹綱引用關係
指導教授(外文):Shiann-Shiun JengShaou-Gang Miaou
學位類別:碩士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:71
中文關鍵詞:串聯積分梳狀濾波器數位中頻接收機軟體定義無線電
外文關鍵詞:cascaded integrator-comb filterdigital IF receiverSoftware defined radio
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  • 被引用被引用:3
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國際通訊聯盟(ITU)所制定之IMT-2000系統目標在於建立一個可全球漫遊、跨系統、跨網路的無縫隙之第三代行動通訊標準,並須提供與現有第二代行動通訊系統相容的需求。然而不同系統間的架構存在編/解碼、解/調變、頻寬和資料傳輸速率等差異,因此第三代行動通信系統的設備需具有相容性(Compatibility)、使用彈性(Flexibility)、可重構性(Reconfigurability)和可升級性(Upgradability)的多功能需求。
本論文首先介紹軟體定義無線電系統,在考量現有硬體技術之限制,找出一可實現之軟體定義無線電收發機架構,再說明本論文所設計適用於軟體定義無線電收發機之數位中頻接收機,並利用串聯積分梳狀濾波器(cascaded integrator-comb; CIC)作抽選(decimation)濾波器,並加上串聯積分梳狀濾波器之補償濾波器完成數位中頻可程式化降頻器之設計。基於FPGA硬體實現的考量,將原先浮點(Floating-point)運算架構之系統以定點(Fixed-point)運算的設計來取代,評估所需運算、可能之字元長度(word length)及數位電路之複雜度,找出其最佳化之架構。最後透過MAX + PLUSⅡ完成可程式化降頻器之可共用元件電路閘層(Gate-level)的設計。
本論文將有助於建立更彈性化、模組化且多重標準(Multi-standard)的軟體定義無線電通訊系統。

The objective of the IMT-2000 system drawn up by ITU is to establish a seamless third generation mobile communication standard with the function of global roaming across any systems and networks. It also provides the compatibility with the second mobile communication systems. However, the transmission schemes, such as coding/decoding, modulation/demodulation, signal bandwidth and data transmission rates, among mobile communication systems are different. Therefore, the 3G mobile communication systems should be compatible, flexible, reconfigurable and upgradable to various mobile communication systems.
The thesis first introduces the software defined radio system, explores the practical structure of software defined radio transceiver under the limitation of existing hardware techniques and reveals the digital IF receiver technique used in this thesis. Then, we will use cascaded integrator-comb filter for decimation and its compensative filter to design the digital IF programmable downconverter. For the FPGA hardware implementation, we will replace the original floating-point operation system with the fixed-point operation. The required sampling rate, arithmetic operation, effective word length, and the complexity of digital circuits will be evaluated and optimized. Finally, we will accomplish the common component gate-level design of the programmable downconverter with MAX+PLUS II and download the programs to the ALTERA FLEX serial chips.
This thesis is very helpful to build flexible, multi-standard software defined radio communication systems.

摘要I
AbstractII
致謝III
目錄IV
圖目VI
表目X
第一章 緒論1
1.1 研究背景1
1.2 研究動機與目的2
1.3 研究方法與步驟3
1.4 論文架構4
第二章 軟體定義無線電收發機5
2.1 軟體定義無線電論壇的開放式無線電平台架構5
2.2 軟體定義無線電系統架構發展10
2.3 軟體定義無線電收發機架構12
2.3.1 外差接收機12
2.3.2 直接轉頻接收機14
2.3.3 數位中頻接收機15
2.3.3.1 類比/數位轉換器之考量17
2.3.3.2 可程式化數位降頻器19
第三章 數位中頻可程式化降頻器之設計22
3.1 數位中頻架構22
3.2 次取樣法23
3.3 數位降頻器之設計27
3.3.1 串聯積分梳狀濾波器28
3.3.2 CIC濾波器之補償濾波器考量32
3.4 各種系統規格之設計實例34
第四章 數位中頻接收機之硬體實現及考量41
4.1 數位電路設計時之定點模擬41
4.1.1 FIR濾波器定點運算考量41
4.1.2 數位混波器之定點運算考量45
4.1.3 系統定點運算模擬52
4.2 FPGA/CPLD架構說明55
4.3 FIR濾波器實現57
4.4 數值控制震盪器之實現61
第五章 結論與展望66
5.1 結論66
5.2 未來展望67
參考文獻68
作者簡介71

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