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研究生:陳佑任
研究生(外文):Yu-Ren Chen
論文名稱:IC封裝製程中的模流分析與金線偏移
論文名稱(外文):Mold-Flow Simulation and Wire Sweep in IC Encapsulation
指導教授:鍾文仁鍾文仁引用關係
指導教授(外文):Wen-Ren Jong
學位類別:碩士
校院名稱:中原大學
系所名稱:機械工程研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:英文
論文頁數:82
中文關鍵詞:金線密度模流分析金線偏移
外文關鍵詞:Wire SweepWire DensityBGAQFPC-MOLD
相關次數:
  • 被引用被引用:4
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金線偏移已被確認為是微電子構裝在轉移成型製程中最主要的缺陷之一。當IC元件朝向薄型元件與高密度發展的同時,金線偏移分析的探討亦將變得更困難且具挑戰性。
本文將要藉著CAE模擬,探討在IC構裝中模流的流動情形以及金線偏移量的預測。並藉著對形狀因子的控制來探討金線密度對於流動波前的影響,將之整理成一對於金線偏移分析的結論。此外,本文並提出新的金線偏移整合分析軟體(Auto IC),Auto IC整合了模流分析(C-MOLD)與結構分析(ANSYS),不但可準確的預測IC構裝中的金線偏移現象,更簡化了實際分析的過程。最後並藉著對三組高腳數IC(BGA與QFP)的實際分析案例來驗證本文。

Wire sweep has been recognized as one of the major defects in the encapsulation of microelect- ronic chips by the transfer molding process. As thinner and denser IC packages become, wire-sweep analysis becomes more challenging and troublesome.
This thesis will study the reactive flow in IC encapsulation by the CAE simulation (C-MOLD) and the wire-sweep phenomena. In fact, it consi- ders the effect of wire density (number of wire) by controlling the shape factor to simulate the flow resistance and has a better solution for wire-sweep prediction. Besides, the newly deve-loped CAE tool (Auto IC) will be introduced. It combines global flow analysis (C-MOLD) and stru-cture analysis (ANSYS), not only to predict the wire sweep accurately but also simplify the process for integrated analysis. Finally, three study cases for high pin-count packages (BGA and QFP) are used to verify the research.

CHINESE ABSTRACT............................................I
ABSTRACT...................................................II
ACKNOWLEDGEMENT...........................................III
TABLE OF CONTENTS..........................................IV
LIST OF FIGURES...........................................VII
LIST OF TABLES............................................XIV
CHINESE ABSTRACT OF EACH CHAPTER...........................XV
1. INTRODUCTION.......................................... ..1
1-1Preface............................................1
1-2Problems of Wire Sweep.............................9
1-3Literatrue Review.................................10
1-4Research Goal.....................................11
1-5Structure of Presentation.........................11
2. THEORETICAL ANALYSIS....................................12
2-1Theoretical Analysis for Wire Sweep...............12
2-1-1Global-Flow Analysis (Effect of Wire Density).....13
2-1-2Local-Flow Analysis (Lamb’s Model)...............15
2-1-3Wire-Deformation Analysis.........................16
2-2C-MOLD Reactive Molding...........................16
2-2-1The Mathematical Models...........................17
2-2-2Geometrical Modeling of Cavity Model..............22
2-2-3Gettingthe Element Data and Normal Thickness......23
2-3Wire-Sweep Calculations...........................25
2-3-1L. T. Nguyen Analytical Approach..................25
2-3-2Circular Arch Approach............................27
2-3-3ANSYS Numerical Approach..........................28
3. CAE TOOL (AUTO IC)........................... ........30
3-1About Auto IC.....................................30
3-2Wire-Sweep Analysis Using Auto IC.................31
3-2-1Input the C-MOLD File.............................33
3-2-2Input the Wire Information........................34
3-2-3Wire-Sweep Calculation............................38
3-2-4Output of Solutions...............................40
4. SIMULATION AND EXPERIMENTAL VERIFICATION................43
4-1Case I:SAMPO BGA 436.............................43
4-1-1Geometrical Model.................................43
4-1-2The Material Properties and Process Conditions....47
4-1-3Verification of Melt-Front Advancement............48
4-1-4Simulation and Verification of Wire Sweep.........51
4-1-5Discussion........................................53
4-2 Case II:SPIL BGA 492L..............................54
4-2-1Geometrical Model.................................54
4-2-2The Material Properties and Process Conditions....60
4-2-3Verification of Melt-Front Advancement............61
4-2-4Simulation and Verification of Wire Sweep.........64
4-3 Case III:SPIL QFP 208L.............................67
4-3-1Geometrical Model.................................67
4-3-2The Material Properties and Process Conditions....71
4-3-3Verification of Melt-Front Advancement............72
4-3-4Simulation and Verification of Wire Sweep.........74
4-3-5Investigation of Material Properties..............76
5. CONCLUSIONS AND FUTURE WORK.............................81
5-1Conclusions.......................................81
5-2Suggestion for Future Work........................82
REFERENCES.................................................83
APPENDIX A CIRCULAR ARCH..................................85
VITA.......................................................87

[1] L. T. Manzione,“Plastic Packaging of Microelectronic Devices”, Van Nostrand Reinhold, New York, 1990.[2] R. J. Hannemann, A. D. Kraus and M. Pecht,“Semiconductor Packaging, A Multidisciplinary Approach”, John Wiley & Sons, New York, 1994.[3] J. H. Lau,“Ball Grid Array Technology”, McGraw-Hill, New York, 1995[4] J. H. Lau,“Flip Chip Technologies”, McGraw-Hill, New York, 1995.[5] L. T. Nguyen and F. J. Lim,“Wire Sweep During Molding of Integrated Circuits”, in 40th ECTC, pp. 777-785, 1990.[6] S. Han and K. K. Wang,“A Study on Wire Sweep in Encapsulation of Semiconductor Chips Using Simulated Experiments”, Transactions of the ASME, Vol. 117, pp. 178-184, September 1995.[7] A. A. O. Tay, K. S. Yeo and J. H. Wu,“Wirebond Deformation During Molding of IC Packages”, ASME Journal of Electronic Packaging, Vol. 117, pp. 14- 20, 1995.[8] H. Chai and Y. Zohar,“Unsteady Wire Sweep Due to Transfer Molding in a 160L QFP Package”, ASME Journal of Electronic Packaging, Vol. 121, pp. 127- 134, June 1999.[9] H. Chai and Y. Zohar,“Wire Sweep Due to Transfer Molding in a 160L QFP Package Under Steady-State Conditions”, ASME Journal of Electronic Packaging, Vol. 121, pp. 137-142, September 1999.[10] H. Lamb,“Hydrodynamics”, Cambridge University Press, London, 1945.[11] L. S. Turng,“Computer-Aided Engineering (CAE) for the Microelectronic Packaging Process”, Advances in Computer-Aided Engineering (CAE) of Polymer Processing, Ed. K. Himasekhar, V. Prasad, T. A. Osswald, and G. Batch, MD-Vol. 49/HTD-Vol. 283, pp. 191-208, ASME 1994.[12] V. W. Wang, K. K. Wang and C. A. Hieber,“An Interactive Simulation of Cavity Filling in Injection Molding with Color Graphics”, SPE Technical Papers, Vol. 31, pp. 826-830, May 1985.[13] C-MOLD,“C-MOLD Reactive Molding User's Guide”, C-MOLD, Ithaca, 1995.[14] C-MOLD,“C-MOLD Reactive Molding and Microchip Encapsulation Training Guide”, C-MOLD, Ithaca, 1999.[15] F. Su, R. Lu and J. Fan,“The Application of Cross-Flow Modeling Techniques for TSOP II 54L LOC Packaging”, 1998 C-MOLD Asia/Pacific Microchip Encapsulation Users’ Conference, 1998.[16] L. T. Nguyen, A. Danker, N. Santhiran and C. R. Shervin,“Flow Modeling of Wire Sweep During Molding of Integrated Circuits”, ASME Winter Annual Meeting, November 1992.[17] R. J. Roark and W. C. Young,“Formulas for Stress and Strain”, McGraw- Hill, New York, 1975.[18] M. H. Naitove and J. DeGraspari,“Mold Analysis Make the Grade”, Plastic Technology, pp. 62-73, April 1992.[19] W. R. Jong and Y. L. Chen,“Integrated Design Module for Wire Sweep in IC- Chip Encapsulation”, SPE Technical Papers, Vol. 44, pp. 1206-1210. May 1998.[20] SolidWorks,“SolidWorksÒ 2000 User's Guide”, SolidWorks, 1999.

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