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研究生:李英翰
研究生(外文):Ying Han Lee
論文名稱:底電極薄膜電晶體研究與分析
論文名稱(外文):Research and Analysis of Undergate Thin Film Transistors
指導教授:李中夏李中夏引用關係
指導教授(外文):C.H. Lee
學位類別:碩士
校院名稱:大葉大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:英文
論文頁數:117
中文關鍵詞:複晶矽薄膜電晶體通道長度調變Kink 效應汲極偏壓誘使晶粒邊界位能降低
外文關鍵詞:Poly-silicon Thin Film TransistorsChannel Length Modulation (CLM)Kink Effect (KE)Drain Induced Grain Boundary Potential Barrier Lowering (DIBL)
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摘要
最近,複晶矽薄膜電晶體由於其廣泛應用在印表頭及成像器及平面顯示器上而受到廣泛的注意。傳統上,複晶矽薄膜電晶體有一層絕緣基板及大約12伏特的操作電壓,同時其電特性和複晶矽材料的特性也有極大的關聯。所以,我們不能以傳統上的MOSFET元件模式來描述複晶矽薄膜電晶體元件的操作。到目前為止,很少研究是針對複晶矽薄膜電晶體的元件模式,特別是已發展在MEDICI,TSUPREM4,及AIM-SPICE電路模擬器上的I-V及C-V模式更是付之闕如。最近,部分應用在電路上的低溫複晶矽薄膜電晶體的論文已經發表,但是卻少有論文將溫度效應考慮在電路模式。尤其,更缺乏有關具有溫度效應的複晶矽薄膜電晶體模式建立到商用的電路模擬器上。
本論文嘗試發展一套以物理基礎的複晶矽薄膜電晶體的I-V及C-V模式。首先, 必須發展出一套複晶矽薄膜電晶體的元件模式以及其中參數的萃取方式,參數萃取主要由實驗資料而得,得到之後再帶回所發展德模式中驗證其正確性。所引用的數據主要為一下電極的TFT元件結構,閘極氧化層厚度為1000Å,通道長度從1μm到6μm,且是低溫製程。經由上述步驟所得到的模式已放入SPICE電路模擬器中從而預測測及分析複晶矽薄膜電晶體的電路特性。
在本論文中,我們將描述一個模式,此模式應用在次臨界到飽和區間都是可微分且連續,因此是一個非常適用於加入MEDICI,TSUPREM4,AIM-SPICE 電路模擬器。通道長度調變、速度飽和效應、Kink 效應、溫度效應、閘極偏壓誘使晶粒邊界位能降低(GIBL)、汲極偏壓誘使晶粒邊界位能降低(DIBL)、熱載子效應(Hot Carriers Effect)及溫度相依效應將被我們所探討與模式化。

Abstract
Recently , Poly-silicon Thin Film Transistors have received extensive attention for their potential application in the printhead , imager , large-size active-martix liquid crystal display (AMLCD) . Typically , TFT operates with a floating substrate and the operation bias is about 12V . Moreover , the characteristics of TFT are severely affected by material properties of poly-silicon . As a result , the characteristics of a TFT cannot be accurately modeled by the common bulk MOSFET model in SPICE . Quite a few circuit models for low temperature ploy-silicon TFT have been reported, but very few of them took the temperature effect into account . So far , none have been implemented into commercially available circuit simulator with temperature dependent features .
The work attempt to develop a physically-based analytical current-voltage model and an instrinsic capacitance-voltage model of poly-Si TFT for circuit simulation . First , we have developed a set of programs including I-V and C-V models and parameter extraction methods . The model parameters are extracted from the experimental data and then substituted back into the developed models . The accuracy of these models were successfully implemented in MEDICI , TSUPREM4 , AIM-SPICE . The experimental data used here are measured from a AMLCD wafer with p-substrate and undergate structure . The device models are finally implemented in the AIM-SPICE circuit simulator to predict and analyze the circuit performance of poly-si TFT .
A model , is described for applications from the subthreshold to saturation regions that is continuous and differentiable , is suited for MEDICI , TSUPREM4 , AIM-SPICE circuit simulator , in this thesis . Channel Length Modulation (CLM) , Velocity Saturation (VS) , Kink Effect (KE) , Temperature Dependence Effect (TDE) , Drain Induced Grain Boundary Potential Barrier Lowering (DIBL) , Gate Induced Grain Boundary Potential Barrier Lowering (GIBL) , Hot Carriers Effect (HCE) are discussed and modeled .

CONTENTS
封面內頁
簽名頁
授權書...........................iii
中文摘要 ..........................iv
ABSTRACT ..........................vi
ACKNOWLEDGEMENT .....................viii
CONTENTS ..........................ix
FIGURE CAPTIONS ...................... xi
TABLE CAPTIONS ......................xvi
LIST OF SYMBOLS......................xvii
Chapter 1 Introduction....................1
Chapter 2 Physical properties of Undergate TFT........5
2.1 The Traditional FET and TFT ...............5
2.2 Amorphous and Poly-Silicon................6
2.3 Channel Length Modulation ................8
2.4 Models of Advanced TFT .................10
2.5 Kinds of TFT LCD’s Active Channel Material.......12
2.6 Materials of Active Channel...............13
Chapter 3 The Analytical Model for the Intrinsic Amorphous Silicon Undergate TFT....................24
3.1 The Empirical Model of Trapped Charge..........24
3.2 The I-V Model of Amorphous-Si TFT............26
3.2.1 Long Channel Current-Voltage Characteristics.....28
3.3 The C-V Model of Amorphous-Si TFT............35
Chapter 4 The Analytical Model for the Intrinsic Poly-Silicon Undergate TFT........................45
4.1 The I-V Model of Poly-Si TFT ..............45
4.2 The I-V Model of Poly-Si TFT ..............50
Chapter 5 Results of Experimental Simulations........55
5.1 Overview of Simulation Programs.............55
5.1.1 Introduction of TSUPREM-4 ...............55
5.1.2 Introduction of MEDICI 4.0...............57
5.1.3 Introduction of AIM-SPICE 3.5 .............59
5.2 Parameters of Simulation : Materials of Active Channel..60
5.3 Parameters of Simulation : Insulators..........62
5.4 Parameters of Simulation : Length, Width and Thickness..62
5.5 Parameters of Simulation : Temperature .........63
5.6 Experimental Simulations ................64
Chapter 6 Conclusion....................107
References.........................111

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