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研究生:賴曉輝
研究生(外文):Lai Hsiao Hui
論文名稱:數位式波束成形接收機硬體架構之研究與設計
論文名稱(外文):Research and design in hardware architecture of digital beamforming receiver
指導教授:黃其泮
指導教授(外文):Chi-Pan Hwang
學位類別:碩士
校院名稱:大葉大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:81
中文關鍵詞:波束成形數位降頻器帶通訊號取樣數位式接收機
外文關鍵詞:BeamformingDigital Down ConverterBand-pass SamplingDigital Receiver
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本論文主要對數位式波束接收機硬體架構之研究與設計,波束成形接收機是由一組陣列天線所構成,它使我們能在無線電環境中達成空間多重存取(Space Division Multiple Access, SDMA)。透過適應處理器偵測每一個訊號源所抵達的入射角度(Direction Of Arrival, DOA),估測出最佳權重向量,使環境空間中產生多指向的波束,因此適應波束成形能增加系統通訊容量。空間多重存取(SDMA)主要的技術之一是智慧型天線,智慧型天線可以改善下列幾點:(1)增加頻譜使用率和系統的容量(2)減少多重路徑的干擾(3)消除同頻的干擾(4)範圍的擴大。
本文中介紹使用帶通取樣法(band-pass sampling)在中頻取樣的軟體無線電架構,我們完成使一台電腦同時能控制多組數位降頻器的控制軟體和介面電路,控制軟體是由BCB(Borland C++ Builder)所寫成視窗介面軟體,包含三個視窗介面:詳見任一組的控制參數介面、同時監控十八組數位降頻器預降頻率大小介面和微調介面。介面電路上有8 bits調址器共有256位址可使用,來達到控制多組數位降頻器的目的。以高階硬體語言(VHDL)來描述DBF(Digital Beamforming)電路,再以Xilinx 4036-3晶片完成DBF實現。

The thesis focuses on the research and design of digital beamforming receiver’s hardware architecture. The receiving front-end consists of an array of sensors (antennas) by the beamforming techniques, we can arrive at the goal of space division multiple access in wireless environment. The adaptive processor detects the direction of arrival (DOA) of each source spreading in space and estimates the optimal weight vector. Consequently, adaptive beamforming can be used to increase system capacity. One of the main issues in Space Division Multiple Access (SDMA) is a technique of smart antenna. The smart antenna can improve performance in several ways:(1) To increase spectral efficiency and system capacity.(2) To reduce multi-path interference.(3) To combat co-channel interference(CCI).(4) Range extension.
In this text, we apply the band-pass sampling theorem for IF sampling of the architecture of software radio. Furthermore, we completed interface-circuit and control-software which can control multi-digital down converter in one computer simultaneously, and realize the Digital Beamforming(DBF) module by Field Programmable Gate Array (FPGA). The control-software of view interface software is written by Borland C++ Builder (BCB) . It contains three view form:(1) To explain any Digital Down Converter (DDC) magnitude interface (2) To monitor eighteen DDC magnitude interface simultaneously (3) tuning interface. The eight-bits adjust-addresser on the interface circuit can be used total two hundred fifty-six addresses. This reaches purpose of control multi-DDC. The Very High Description Language (VHDL) describes DBF circuit to accomplish DBF by Xilinx 4036-3’s chip.

目錄
封面內頁
簽名頁
授權頁.......................iii
中文摘要.......................iv
ABSTRACT.......................v
誌謝.......................vii
目錄.......................viii
圖目錄.......................x
表目錄.......................xiii
第一章 緒論.......................1
1.1 數位式波束成形接收機簡介..............1
1.2 研究背景.......................4
1.3 研究動機.......................5
1.4 論文架構.......................5
第二章 取樣原理.....................7
2.1 取樣原理.......................7
2.2 低通訊號取樣(Sampling Low-Pass Signal)........13
2.3 帶通訊號取樣(Bandpass Sampling)............15
2.4 HI5767介紹.......................22
第三章 數位降頻器分析...................27
3.1 前言.........................27
3.2 正交(Quadrature )取樣.................30
3.3 數位升頻器.......................31
3.4 數位降頻器.......................38
3.5 數位式降頻模組....................46
3.6 介面軟體.......................48
3.7 介面電路.......................51
第四章 DBF之實作.....................55
4.1 DBF特色.......................55
4.2 功能.........................56
4.3 實作方法.......................58
第五章 模擬與實際量測...................61
5.1 模擬.........................61
5.2 實際量測.......................70
第六章 結論與未來展望...................75
6.1 結論.........................75
6.2 未來展望.......................76
參 考 文 獻.......................78

參 考 文 獻
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