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研究生:李宗穎
研究生(外文):Tsung-Ying Lee
論文名稱:邏輯核心初期設計階段之收益評估系統
論文名稱(外文):A Profit Eavluation System (PES) for Logic Cores at Early Design Stage
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:67
中文關鍵詞:良率錯誤函蓋率內建自我測試容錯電路易測試設計收益經濟分析
外文關鍵詞:yieldFault CoverageBISTFault-Tolerant CircuitDesign-for-TestabilityProfitEconomic Analysis
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我們針對積體電路設計者提供了一個收益評估系統,這個系統將可以幫助設計師在設計規格的限制與一些製程參數資料的要求下計算出產品的良率與測試計劃,而我們根據此系統輸出結果的良率與錯誤函蓋率便可求得產品的最大收益。在本系統中,我們考量到兩個額外的電路設計架構,一個是加入內建自我測試電路,另一個是加入容錯電路。加入內建自我測試之設計會伴隨著一些成本,如矽晶片面積、接腳、以及效能降低等負擔。但內建自我測試卻能降低診斷及測試機台的成本,此外,還可以降低測試所需的時間。另外,加入容錯電路雖然會增加矽晶片的面積,但卻可以有效的提升產品的良率,在我們的評估系統中,提供了兩階層的容錯電路架構,第一層是針對晶片中模組電路的容錯,第二層則是針對模組電路下單元電路的容錯。我們考慮內建自我測試與容錯電路對於設計驗證及測試開發所需時間的影響,提出它們的成本與收益模型。
我們自行假設出一組參數來做樣本模擬實驗,我們利用此樣本來實驗有關加入內建自我測試對電路測試成本的影響以及加入容錯電路對電路良率的影響,並考量要加入多少的容錯電路可以得到最大的收益。實驗結果顯示當電路加入內建自我測試可以有效提升產品收益,此外,一層容錯電路的收益在此樣本中比兩層容錯電路所得的收益還高。
我們將此系統架構在WWW全球資訊網下,是一個超大型積體電路收益評估分析系統,包含了四個經濟模型以及一套測試方法,這套系統可以幫助超大型積體電路之專案經理或設計師姑在產品下線前估算成本與收益。
In this paper, we propose a Profit Evaluation System (PES) for IC designers. This system will help designers to determine the yield and test plan when specified quality level is given. Type of circuit fabric and raw manufacturing data (i.e., wafer size, wafer cost, defect density and distribution) are given for the system. In our system, we consider two circuit design architecture, BIST and fault-tolerant circuits. Typical costs associated with BIST are silicon area overhead, pin-count overhead, and performance loss. However, BIST can reduce diagnosis and tester-related costs. In addition, fault-tolerant circuits also increase silicon area overhead but it increase yield effectively. We provide two-level redundancies into our system. Then we propose cost and profit models for BIST and fault-tolerant circuits.
The outputs of the system are the values of yield and fault coverage that will generate maximal profit. Different yield models and cost models are selectable for the users. Experimental results show that the system can find the optimal yield and test plan for generating the maximal profit.
We incorporate the proposed models in our Profit Evaluation System (PES) project. It is a WWW-based consisting of a set of economic models and a test methodology. VLSI project managers and designers can be assisted by PES when they need to evaluate the costs and profit before products shipped.
1. Introduction1
1.1Economics of Design-for-Yield……………………………………2
1.2Economics of Design-for-Testability…………………………………………...3
1.2.1 Cost Effects of Test Related Parameters………………………………….4
1.2.2 Built-In Self-Test………………………………………………………….5
1.3Previous Works………………………………………………………………….6
1.4Profit Evaluation System………………………………………………………..8
2. Economic Models of PES 9
2.1 Yield Model and Redundancy Analysis………………………………………...9
2.1.1 Chip Architecture………………………………………………………..10
2.1.2 Yield Model Estimation………………………………………………….11
2.2 Test Cost Model………………………………………………………………..13
2.3 Development Cost Model……………………………………………………...18
2.3.1 Design Model……………………………………………………………18
2.3.2 Test Development Model………………………………………………..19
2.3.3 Verification Model……………………………………………………….19
2.4 Profit Prediction Model………………………………………………………..20
3. Advanced — Yield Improvement with Two — Level Redundancies 26
3.1 Yield Analysis for Two-Level Redundancies………………………………….28
3.2 Evaluation of the Optimum Number of Cell-Level Redundancy……………...30
4. System Development 33
4.1 System Models.……….……………………………………………………….33
4.2 Analysis Flow chart…….………………………………………………...……35
4.3 User Interface…….……………………………………………………………36
5. Experimental Results and Discussion 38
5.1 System Parameters & Assumptions…………………………………………...38
5.2 Yield and Test Plan for One-Level Architecture………………………………40
5.2.1 Case studyⅠ: Variation of Circuit Structure……………………………42
5.2.2 Case study Ⅱ: Variation of Defect Density………………………….…44
5.2.3 Case study Ⅲ: Variation of Chip Area……………………………….…46
5.2.4 Case study Ⅳ: Variation of Number of Wafer per Lot……………….…48
5.3 Yield and Test Plan for Two-Level Architecture………………………………51
5.3.1 Case studyⅠ: Variation of Circuit Structure……………………………53
5.3.1.1 Module Structure Unchanged…………………………………...53
5.3.1.2 Module Structure Changed……………………………………...54
5.3.2 Case study Ⅱ: Variation of Defect Density………………………….…57
5.3.3 Case study Ⅲ: Variation of Chip Area……………………………….…58
5.3.4 Case study Ⅳ: Variation of Number of Wafer per Lot……………….…60
6. Conclusions and Future Works 62
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