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研究生:李建宗
研究生(外文):Chen-Chun Lee
論文名稱:二維離散週期性小波轉換之高效率非分離式超大型積體電路架構
論文名稱(外文):An Efficient Non-Separable VLSI Architecture for 2D Discrete Periodized Wavelet Transform
指導教授:黃有榕洪金車
指導教授(外文):Yu-Jung HuangKing-Chu Hung
學位類別:碩士
校院名稱:義守大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
中文關鍵詞:進階運算元相關演算法超大型積體電路二維離散週期性小波轉換即時處理
外文關鍵詞:AOCAVLSI2D DPWTreal-time processing
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本論文提出一基於AOCA演算法之二維離散週期性小波轉換(2D DPWT)VLSI架構。由於採用2D之濾波參數及利用OCA運算子之間的鏡射效應,使得此一新的VLSI架構相較於其他傳統的2D DWT VLSI架構具有較少的乘法器及暫態資料位元數。此架構的主要特色在於其採用並行資料處理的方式,因此具有100﹪的硬體使用率的特性及非常短的時間延遲。此外又因為我們採用了特殊的homeomorphic濾波器,故對於邊界值資料的處理得以簡化也因此使得完美影像重建得以實現。此一新架構亦可適用於即時處理之應用。

In this paper, a pipeline-parallel VLSI architecture based on the AOCA algorithm is developed for the 2D discrete periodized wavelet transform (DPWT). Due to adapting the 2D filter coefficient and using the mirror effect between the OCA operators, the new architecture needs less multipliers and bus width than the traditional architectures. The main advantages of this VLSI architecture is by using parallel data processing, so it has 100% hardware utilization and short latency. Moreover we use special homeomorphic filter, so it simplizes the boundary data processing and makes image perfect reconstruction realize.The new VLSI architecture also can be suitable for real-time applications.

目 錄
中文摘要…………………………………...………………..…I
英文摘要…………………………………………...……...….III
致謝…………………………………………………………...V
目錄………………………………………………………...…VI
圖目錄……………………………………………………….VIII
表目錄………………………………………………………...XI
第一章序 論..………………………………………...…….1
1-1 背景簡介…………………...…………………1-1
1-2 研究動機…………………………...…………1-2
1-3 論文架構…………………………………...…1-3
第二章二維離散週期性小波轉換之快速演算法….…2
2-1 線性代數上的觀念……………………...……2-1
2-2 多重解析度分析……………...………………2-4
2-3 1D & 2D小波轉換之概念………...……….2-11
2-4 二維離散週期性小波轉換……………….....2-16
2-5 使用運算元演算法實現2D DPWT………...2-17
第三章AOCA-BASED超大型積體電路架構……..….3
3-1 目前已存在的2D DPWT VLSI架構之回顧\
……………………………………………………..3-1
3-2 轉換係數的分析…………………………...…3-5
3-3 超大型積體電路之架構………...……………3-8
3-4 與其他電路架構之比較………………...…..3-18
第四章電路模擬之結果與驗證……………..…….…….4
4-1 設計流程………………………………...……4-1
4-2 輸入級Stage Switchs之驗證…………...……4-2
4-3 平行處理乘法器(PMs)之驗證………….….4-4
4-4 列累加器之驗證……………………………...4-5
4-5 行累加器之驗證………………..…………….4-6
4-6 邊界值資料電路之模擬與驗證……………...4-9
4-7 2D DPWT之VLSI電路模擬及驗證………..4-13
第五章電路合成及電路佈局……………...……………..5
5-1 重要電路架構…………..…………………….5-1
5-2 電路合成……………………..……………...5-10
5-3 電路佈局結果……………………..………...5-12
第六章結論及未來研究方向…………………...………..6
參考文獻………………………………………………….....R-1

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[21]曾友信,’’離散小波轉換之超大型積體電路架構之研究,”高雄工學院電機工程研究所,86學年度碩士論文
[22]王嘉明,’’二維離散週期性小波轉換之非分離式超大型積體電路架構之實現,”義守大學電子工程研究所,87學年度碩士論

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