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研究生:蘇倍興
研究生(外文):Bei-Xing Su
論文名稱:低通濾波之離散希爾伯特轉換系統之特殊應用積體電路製作
論文名稱(外文):Implementation of Low Pass Filter of Discrete Hilbert Transform System
指導教授:黃有榕陳志良陳志良引用關係
指導教授(外文):You-Rong HuangZhi-Liang Chen
學位類別:碩士
校院名稱:義守大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:90
中文關鍵詞:單旁波帶調變希爾伯特轉換抽值濾波器多重相位分解線性相位
外文關鍵詞:Single side-band modulationhilbert transformdecimatorpoly-phase dissolutionlinear phase
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摘要
由於單旁波帶調變系統屬於窄頻調變因此對於雜訊的抵抗性也相對的較低,也因此我打算製作一個低通濾波的離散希爾伯特轉換轉換系統來解決這個問題。這個系統主要由一個抽值濾波器及一個離散希爾伯特轉換器所組成。首先利用抽值濾波器可衰減雜訊之功能來濾除雜訊,再把訊號送入離散希爾伯特轉換器中作處理。對於抽值濾波器我打算以多重相位分解的觀念來推導其硬體架構,這種架構具有減少輸入訊號運算量的功能。而離散希爾伯特轉換器我打算以線性相位的架構來製作,這種架構由於有係數共享的特性因此可減少乘法器及加法器的運算。上述所提到硬體架構我已用Verilog Code編寫完畢,並以Altera模擬驗證成功,而且也已經成功的利用Synopsys把邏輯電路成功的合成出來。(關鍵字:,,,,

ABSTRACT
Because single side-band modulation system is narrow band modulation it,s rejection of noise is lower. I think of making a discrete hilbert system of low pass filtering. This system consist of decimator and discrete hilbert transformer. First decimator is used of reducing noise. Secondary push the output signal of decimator into the hilbert transformer. For decimator I think that the ideal of poly-phase dissolution to find hardware architecture. Poly-phase dissolution can reduce operation of circuit. For discrete hilbert transformer I think that use architecture of linear phase to design the hardware architecture. The hardware architecture has the advantage of coefficient sharing. So it can reduce the operation multiplication and addition. I have used verilog code to design the Hilbert transformer and decimator successfully. And I have used Altera to simulate them successfully. Finally I use Ssnopsys to synthesis the logic circuit successfully.

封面
摘要
目錄
圖目錄
表目錄
第一章序論 1-1
1.1前言 1-1
1.2歷史回顧 1-2
1.3研究動機 1-3
1.4論文之架構 1-5
第二章 抽值濾波器與離散希爾伯特轉換之數學理論 2-1
2.1抽值濾波器之理論 2-1
2.2複數序列之間之離散希爾伯特轉換之理論 2-12
第三章離散希爾伯特轉換器之應用 3-1
3.1帶通取樣之應用 3-1
3.2單旁波帶調變之應用 3-4
第四章抽值濾波器及希爾伯特轉換器所使用之演算法 4-1
4.1凱瑟加窗法 4-1
4.2線性相位演算法 4-5
4.3 FIR平行演算法 4-7
第五章抽值濾波器與希爾伯特轉換器之硬體架構 5-1
5.1抽值濾波器 5-1
5.2離散希爾伯特轉換器 5-10
5.3簡化係數乘法之結構 5-16
5.4量化誤差之分析 5-17
第六章特殊應用積體電路(ASIC)製作 6-1
6.1特殊應用積體電路製作流程 6-2
6.2以Verilog code 實現抽值濾波器與離散希爾伯特轉換器 6-4
6.3以Synopsys作邏輯合成之結果 6-7
6.4以Altera模擬驗證之結果 6-18
第七章結論及未來方發展方向 7-1
7.1結論 7-1
7.2未來方發展方向 7-2
參考文獻

參考文獻
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[2] Williams, T. A., A Systolic IIR Decimator, International Conference on Acoustics, Speech, and Signal Processing, vol. 4,pp.2560-2563,1989.
[3] Kumar, B., and Choudhury, D.R ,and Kumar,A., On the Design of Linear Phase FIR Integrators for Midband Frequencies, Signal Processing, IEEE Transactions on Volume: 44 6 , June 1996 , Page(s): 1378 —1391
[4] Alan, V. O., and Ronald, W. S., Discrete-time signal processing, 2nd ,ISBN 957-21-2096-6.
[5] David, A. P., and Keshab, K. P.,Area-Efficient FIR Digital Filter Implementation , IEEE Trans. Application Specific Systems,pp.93-111,1996
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[8] Miroslav, D., and Dejan, V., and Brian, L., Filter Design For Signal Processing, Signal Process, ISBN 0-201-36130-2,2001.
[9] Hreemann , O., Rabiner, L. R., and Chan, D. S. K.,Optimum Finite Impulse Response Lowpass Digital Filters,Bell System Technical J.,vol52,NO.6,pp. 769-799,July-Augst.1973.
[10] Hanning, R.W.,Digital Filters, 3rd ed.,Prentice Hall, Englewood Cliffs, NJ,1988.
[11] Haykin, S. S. ,Communication Systems,John Wiey and Sons,New York, 2nd ed.,1983.,
[12] Hermann, O., On the Design of Nonrecurise Digital with Linear Phase,Elect Lett., Vol.6,NO.11,pp.328-329,1970.
[13] Chan, D.S.K.,and Rabiner, L.,Analysis of Quantization Errors in the Direct Form for Finite Impluse Response Digital Filters, IEEE Trans.Audio Electtoracoustics, vol.AU-21,pp.354-366,Aug.1973c.
[14] Cavanagh,J.F.,Digitel Computer Arithmetic:Design and Implementation,MacGraw-Hill Book Company,New York,1984.
[15] Chan, D.S.K.,and Rabiner, L.,An Algorithm for Minimizing Round off Noise in Cascade Realizations of Finite Impluse Response Digital Filters ,Bell System Technical J.,Vol.52,NO.3,pp.347-385,Mar.1973b.
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[19] 以MATLAB 透視DSP 作者:蒙以正
[20] Verilog硬體描述語言數位電路設計實務 作者:鄭信源
[21] Logic Syntthesis Design Kit 國家晶片設計中心 July-2000
[22] Cell-Based Physical Design and Verification Training Manual 國家晶片設計中心 July-2000

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