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研究生:徐玉龍
研究生(外文):Paul Shyu
論文名稱:低功率結構式預先計算設計
論文名稱(外文):Structural Precomputation Design for Low Power
指導教授:王行健
指導教授(外文):Sying-Jyan Wang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:43
中文關鍵詞:低功率設計預先計算
外文關鍵詞:low power designprecomputation
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超大型積體電路在最近幾年裡,因為製程技術不斷提昇,執行速度已經快速提昇,單位面積所容納的電晶體也如預期的增加,然而因為可攜式電器的快速成長,電路的功率消耗,已經漸漸比其處理速度受到更多的重視,晶片的低功率的設計需求已經相當普遍,不論是手機、筆記型電腦、數位相機等應用,都希望達到低功率消耗,雖然犧牲了一些速度,或是增加了一些面積,但只要能達到增加使用時間的目的,都是可以接受的。
我們希望藉由電路結構的分析,找出最好的節點,來作預先計算(precomputation),控制輸入暫存器的工作,藉由節點的邏輯值機率,以及可節省的節點數等參數,去計算出期望值,以找出可節省最多功率的節點,來減少電路節點的轉態(transition)。

As the VLSI process technology continuously improves in recent years, the operational speed of a chip increased dramatically, and the number of transistors in a chip also increases greatly as expected. However, as the requirement for portable devices grows, we should pay much more attention to the power consumption in a circuit rather than it’s speed and area, and the need for low power is now evident in the circuit design. In applications like mobile phones, notebook computers, digital camera and so on, the low power consumption is one of the most important design considerations. We may have to sacrifice circuit performance and area to reduce power consumption, but it’s now acceptable since we just want to have a longer operating time of the device.
In the thesis, we try to find out the best precomputation logic from a circuit by calculating a power-saving metric, which is determined from the structural analysis of the circuit’s information like net probability and savable net weight count. As a result, we can decrease the transition count in a circuit by controlling the input registers with the precomputation logic we found.

第一章 簡介1
1.1 研究動機與目標1
1.2 內容大綱 3
第二章 背景知識與相關研究4
2.1 CMOS功率消耗的模型4
2.2 相關研究 9
第三章 系統架構分析13
3.1 架構一 13
3.1.1 機率的計算18
3.1.2 節點的weight20
3.1.3 資料同步 21
3.1.4 必須工作的節點25
3.1.5 重複的節點27
3.1.6 架構一的演算法28
3.2 架構二 31
3.3 架構三 35
第四章 實驗結果與分析38
第五章 結論與未來工作40
參考文獻 41

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[2] A. Mota, J. Monteiro, A. Oliveira, “Power optimization of combinational modules using self-timed precomputation,” in Proc. IEEE Int’l Symp. Circuits and Systems, Vol. 2 , pp. 17 —20, 1998.
[3] Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, “Low-power CMOS digital design,” in IEEE Journal of Solid-State Circuits, Vol. 27, pp. 6-13, April 1992.
[4] M. Damiani, G. De Micheli, “Observability Don’t Care sets and boolean relations,” in IEEE Int’l Conf. Digest of Technical Papers, pp. 502-505, 1990.
[5] Benini, L.; De Micheli, G.; Macii, A.; Macii, E.; Poncino, M.; Scarsi, R. “Glistch power minimization by selective gate freezing,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8 No.3, pp. 287-298, June 2000.
[6] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, secnod ed., Addison-wesley, 1992
[7] Tiwari, V.; Malik, S.; Ashar, P., “Guarded evaluation: pushing power management to logic synthesis/design,” in IEEE Transactions , Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, pp1051 —1060, Oct. 1998.
[8] Kapadia, H.; Benini, L.; De Micheli, G., “Reducing switching activity on datapath buses with control-signal gating,” in IEEE Journal of Solid-State Circuits, Vol. 34, pp. 405 —414, March 1999.
[9] Benini, L.; De Micheli, G., “State assignment for low power disipation,” in IEEE Journal of Solid-State Circuits, Vol. 30, pp. 258 —268, March 1995.
[10] Benini, L.; Siegel, P.; De Micheli, G., “Saving power by synthesizing gated clocks for sequential circuits,” in IEEE Design & Test of Computers , Vol. 11, pp. 32 —41, Winter 1994.
[11] Bellas, N.; Hajj, I.N.; Polychronopoulos, C.D.; Stamoulis, G., “Architectural and compiler techniques for energy reduction in high-performance microprocessors,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, pp. 317-326, June 2000.
[12] Shyh-Jye Jou; I-Yao Chuang, “Low-power globally asynchronous locally synchronous design using self-timed circuit technology,” in Proc. Int’l Symp. Circuits and Systems , Vol. 3 , pp. 1808 —1811, 1997.
[13] Tan, Y.K.; Lim, Y.C., “Self-timed precharge Latch,” in Int’l Symp. Circuits and Systems,. Vol. 1, pp. 566 —569, 1990.
[14] Somasekhar, D.; Roy, K., “Differential current switch logic: a low power DCVS logic family,” in IEEE Journal of Solid-State Circuits, Vol. 31, pp. 981 —991, 1996.
[15] A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of average switching activity in combinational and sequential circuits” in Proc. 29th Design Automation Conf., June 1992, pp. 253-259.
[16] J. Monteiro, S. Devadas, and A. Ghosh, “Retiming sequential circuits for low power,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1993, pp. 398-402.
[17] J. Monteiro, S. Devadas, and B. Lin, “A methodology for efficient estimation of switching activity in sequential logic circuits,” in Proc. 31th Design Automation Conf., June 1994, pp. 12-17.
[18] F. Najm, “Transition density, a stochastic measure of activity in digital circuits,” in Proc. 28th Design Automation Conf., June 1991, pp. 644-649.
[19] K. Roy and S. Prasad, “SYCLOP: Synthesis of CMOS logic for low power applications,” in Proc. Int. Conf. Computer Design: VLSI in Computers and Processors, Oct. 1992, pp. 464-267.
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[21] Z. J. Lemnios and K. J. Gabriel, “Low-Power Electronics,” in IEEE Design & Test of Computers, pp. 8-13, winter 1994.

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