(3.80.6.131) 您好!臺灣時間:2021/05/17 03:51
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:游榮豪
研究生(外文):Rung-Hau You
論文名稱:高速全數位鎖相迴路
論文名稱(外文):High Speed All Digital Phase-Locked Loop
指導教授:張振豪
指導教授(外文):Chen-Hao Chang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:78
中文關鍵詞:全數位鎖相迴路鎖相迴路延遲鎖相迴路相頻偵測器
外文關鍵詞:ADPLLPLLAll Digital Phase-Locked LoopPhase-Locked LoopDLLDelay-Locked LoopPFDPhase-Frequency Detector
相關次數:
  • 被引用被引用:2
  • 點閱點閱:878
  • 評分評分:
  • 下載下載:145
  • 收藏至我的研究室書目清單書目收藏:0
摘要
本篇論文描述一個高速全數位鎖相迴路的架構與設計,使用取樣編碼方式,能在四個參考週期內決定DCO操作模式及輸入信號在十六組頻率區段中的位置並局部修改演算流程與DCO設計,使本電路具有較快的搜尋速度、較短的鎖定時間、較小的Phase Jitter,並可操作在極高的頻率。架構中可分為數位控制振盪器,頻率偵測器、相位偵測器、UP/DN Counter、控制單元、啟動電路、取樣電路、編碼電路、位元指標器、除頻器及相位選擇器等十一個部分。操作程序可分為頻率獲取、相位獲取、頻率維持及相位維持四種程序,利用控制單元執行二元搜尋演算法(Binary Search)改變UP/DN Counter增益,控制DCO輸出,使ADPLL輸出與參考信號一致完成鎖相程序。
模擬結果顯示當DCO分別操作在1.25GHz與2.5GHz時相位差(Phase Error)皆可小於100ps,系統dead zone小於30ps,所需鎖定時間少於34個參考時脈週期(演算法)或1us(實際模擬),鎖定範圍在DCO模式0時為2.3GHz ~ 2.6GHz,模式1時為0.8GHz ~ 1.3GHz,使用製程是TSMC 1P4M 0.35um,操作電壓3V。功率消耗在1.25GHz時為106.1mW,與2.5GHz時為91.46mW。

Abstract
This thesis describes the architecture and design of a high speed all digital phase-locked loop (ADPLL), which uses sample and encode method to decide DCO operation model and frequency region of the input signal in 16 levels. The method can also modify part of algorithm and DCO design. The proposed ADPLL design has characteristics of fast search speed, short frequency locking time, small phase jitter and high operating frequency. This architecture comprises digital controlled oscillator (DCO), frequency detector (FD), phase detector (PD), UP/DN counter, control unit, start circuit, sample circuit, encoder, bit indicator, divider, phase chooser. The phase-lock procedures for this proposed ADPLL are frequency acquisition, phase acquisition, frequency maintenance and phase maintenance. The phase-lock procedures control unit to execute binary search algorithm, which changes UP/DN counter gain and controls the DCO output. When the ADPLL output is in phase with reference clock the phase-lock procedures are accomplished.
The proposed ADPLL is simulated and implemented by the TSMC 0.35μm 1P4M technology. The supply voltage is 3V. The simulation results show that when DCO operates at 1.25GHz or 2.5GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 34 reference clock cycles (algorithm) or 1us (simulation). The lock-in range is 2.3GHz to 2.6GHz in the mode 0 and 0.8GHz to 1.3GHz in the mode 1. The power consumption is 106.1mW at 1.25GHz and 91.46mW at 2.5GHz.

摘要
Abstract
目錄
圖目錄
表目錄
第一章 緒論
1.1 研究動機
1.2 研究方法與流程
1.3 內容大綱
第二章 鎖相迴路簡介
2.1 鎖相迴路種類
2.2 線性鎖相迴路(Linear Phase-Locked Loop)
2.3 數位鎖相迴路(Digital Phase-Locked Loop)
2.4 全數位鎖相迴路(All Digital Phase-Locked Loop)
2.5 軟體式鎖相迴路(Software Phase-Locked Loop)
第三章 架構與流程
3.1 架構概說與演算方式
3.2 系統架構
3.3 系統流程與演算法
3.2.1 頻率獲取(Frequency acquisition)
3.2.2 相位獲取(Phase acquisition)
3.2.3 頻率維持(Frequency maintenance)與相位維持(Phase maintenance)
3.4 系統與錯誤保護
3.5 收斂問題
3.6 鎖定時間
第四章 電路設計
4.1 啟動電路(Start Circuit)
4.2 頻率偵測器(Frequency Detector, FD)與相位偵測器(Phase Detector, PD)
4.3 取樣電路(Sample Circuit)
4.4 編碼電路(Encode)
4.5 UP/DN Counter與位元指標器(Bit Indicator)
4.6 數位控制振盪器(Digital Controlled Oscillator, DCO)與除頻器(Divider)
4.7 相位選擇器(Phase Choice)
4.8 控制單元(Control Unit)
第五章 模擬結果
第六章 結論
參考文獻
附錄A

[1] Roland E. Best, Phase-Locked Loop:Design, Simulation, & Applications, Third Edition, McGraw-Hall Inc., 1993.
[2] 陳光原, The Design and Implementation of a 3.3v 400MHz All Digital Phase-Locked Loop, Master Thesis, Tamkung University,1997.
[3] Jim Dunning, Gerald Garcia, Jim Lundberg, and Ed Nuckolls, “An ALL-Digital Phase-Locked Loop with 50-cycle Lock Time Suitable for High Performance Microprocessors,” IEEE Journal of Solid-State Circuits, Vol.30, no.4, pp.412-422, Apr. 1995.
[4] Won-Hyo Lee, Jun-Dong Cho, Sung-Dae Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge-pump”, Asia and South Pacific -Design Automation Conference, pp.269 -272 , 1999.
[5] Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu and Shen-Iuan Liu, “New dynamic flip-flops for high-speed dual-modulus prescaler”, IEEE Journal of Solid-State Circuits, Vol. 33, no. 10, , pp. 1568 —1571, Oct. 1998.
[6] 楊怡英, The implementation and analysis of an All Digital Phase Locked-Loop, Master Thesis, National Central University,1997
[7] 盛鐸, An All Digital Phase Locked-Loop(ADPLL) with Fast Lock-In Time─Analysis, Implementation and Application, Master Thesis, National Chung Cheng University, 1999
[8] 許騰尹, The Study of All Digital Phase Locked-Loop(ADPLL) and its Applications, Dissertation Thesis, National Chiao Tung University, 1999
[9] 郭隆質, 1.5V 900MHz CMOS Phase Locked-Loop, Master Thesis, National Chung Hsing University, 2000
[10] T.-Y. Hsu, B.-J. Shieh, and C.-y. Lee,“An all-digital phase-locked loop (ADPLL)-based clock recovery circuit,”IEEE J. of Solid-State Circuits, vol.34,no. 8, pp. 1063~1073, August 1999.
[11] 鄭為全, Analysis and Design of the All-Digital Phase-Locked Loop, Master Thesis, National Taiwan University ,1997.
[12] Jen-Shiun Chiang and Kuang-Yuan Chen, “The Design of an All-Digital Phase-Locked Loop with Small DCO Hardware and Fast Phase Lock,” IEEE Transactions On Circuits and Systems-Ⅱ: Analog And Digital Signal Processing, vol.46, NO.7 July 1999
[13] Shyh-Jye Jou, Ya-Lan Tsao and I-Ying Yang. “An All Digital Phase-Locked Loop with Modified Binary Search of Frequency Acquisition,” Electronics, Circuits and Systems, 1998 IEEE International Conference on, vol.2, pp. 195-198, 1998.
[14] 曹亞嵐, All Digital Phase Locked-Loop, Master Thesis, National Central University, 1996
[15] Jen-Shiun Chiang and Kuang-Yuan Chen, “A 3.3v All Digital Phase-Locked Loop with small DCO Hardware And Fast Phase Lock”, Circuits and System, 1998 ISCAS’98 Proceeding of the 1998 IEEE International Symposium on, volume: 3, 1998
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊