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研究生:陳天賜
研究生(外文):T. S. Chen
論文名稱:低電壓CMOS電流模式取樣保持電路的設計
論文名稱(外文):Design of Low-Voltage Current-Mode CMOS Sample-and-Hold Circuits
指導教授:張振豪
指導教授(外文):C. H. Chang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:英文
論文頁數:66
中文關鍵詞:低電壓電流模式取樣保持電流鏡電壓到電流快速傅立葉轉換信號雜訊比解析度
外文關鍵詞:Low-VoltageCurrent-ModeSample-and-HoldCurrent-MirrorVoltage-to-CurrentFFTSNRENOB
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摘 要
本篇論文設計了一個低電壓、電流模式的CMOS取樣保持電路。
提出的電路中包括一對電流鏡電路及低電壓運算放大器,利用運算放大器虛短路的特性,使得在輸入端點的電位可以獨立於輸入信號而維持定值;這樣,輸入信號只要經一個外接電阻和電容串聯組成的電路,便能將輸入為電壓形式的信號轉換成對應的電流形式。其中低電壓運算放大器是由兩個串接的共源極放大器(由MOS電晶體和定電流源組成)來實現的,這種架構可以很輕易地使輸入端點的電壓維持在電源電壓的中點。另外,整個電路只用了兩個互補式電晶體對的開關,並配置成差動組態,它能將開關電晶體引起的穿越效應所造成的誤差降到最小。
所提出的電路是採用TSMC 0.35μm CMOS 1P4M的製程來設計並以Hspice來模擬;結果顯示這個電路操作在1.5V的單一電源下可以達到10位元的解析度、±200μA的輸入信號範圍、小於0.07% 的非線性、在50MHz取樣頻率下的輸入信號頻率為1-MHz和8-MHz時的信號雜訊比分別是58dB和56dB、低於1.7mW的功率消耗及70μm×70μm 的晶片Layout面積。

Abstract
The low-voltage, current-mode, CMOS, sample-and-hold circuit has been designed in this thesis. The proposed circuit includes a pair of current-mirror circuits with low-voltage operational amplifier, which keeps the input node voltage constant and independent of the input signal. Thus, conversion of the input voltage signal to current form that can be done by simply connecting an external resistor and capacitor. The low-voltage operational amplifier is implemented with a cascade MOS transistor and a constant current source in a common-source amplifier configuration, which can easily maintain the input node voltage of the circuit at half of the supply voltage. The proposed circuit uses only two complementary switching transistors in differential form so that the feed-through error caused by the switching transistor is minimized.
The sample-and-hold circuit is designed using the TSMC 0.35μm CMOS 1P4M technology and simulated by Hspice. The simulation results show that the circuit can achieve 10-bit resolution under a single supply voltage of 1.5V. The input signal range is ±200μA. Its nonlinearity is below 0.07%. The signal-to-noise (SNR) is 58 dB and 56dB with 1-MHz and 8-MHz input signal at 50 MHz sampling rates. The power consumption is less than 1.7mW. The area of layout is 70μm×70μm.

Chapter 1 Introduction..…..………………..……………1
1.1 Motivation..………..…………..……..……….1
1.1.1 Analog Design Octagon.....…..….…...……….2
1.1.2 Why Low-Voltage and CMOS.….……...…..………3
1.1.3 Why Current-Mode….…..………………….……...4
1.2 Organization.…….....…..………….…………6
Chapter 2 Performances Definition and Strategies…..7
2.1 Performances Definition.……………………………..7
2.1.1 Acquisition Time..…..……..…………………….8
2.1.2 Aperture Errors……..…..………………………..8
2.1.3 Charge Injections……………………...….………9
2.1.4 Dynamic Range...……………………..….….....10
2.1.5 Feed-through.....………………………………...10
2.1.6 Gain Error. ...………..……….……….……...11
2.1.7 Hold Settling Time....…......……….……...12
2.1.8 Nonlinearity Error…….………………………….12
2.1.9 KT/C Noise……………….………………………...13
2.1.10 SNR and SNDR…………………………….…….……13
2.2 Strategies of Precision Condition..………………14
2.2.1 Dummy Switches……...………………….…..…..15
2.2.2 Complementary Switches……….………………...16
2.2.3 Differential Circuits…………...…...……...17
2.3 Strategies of Speed Condition…..…………………18
2.3.1 On-Resistance of the Switching Transistors…18
2.3.2 Low-Voltage Considerations…….……..……….19
Chapter 3 Design of the Current-Mode Sample-and-Hold Circuits……................................……….21
3.1 Conventional Current-Mirror Circuit.….…..……21
3.2 High-Accuracy Current-Mirror Circuit.…...…….23
3.3 The Proposed Low-Voltage High-Accuracy Current-Mirror Circuit…........….............................….25
3.4 Input Voltage-to-Current Conversion. ……..……27
3.5 The Design of Sample-and-Hold Circuit…..………30
3.6 The Proposed Differential Sample-and-Hold Circuit............................................31
3.7 Modification of Cascode Mirror…..….…….33
3.8 Clock Generator and Clock Booster……….…36
Chapter 4 Simulation and Analysis..…………………..40
4.1 Simulation of the Proposed Circuit….…………..40
4.2 Linearity Measuring………………………....………45
4.3 SNR and ENOB Specifications…….………………….49
4.4 SNR and ENOB Testing by FFT………..…………....52
4.5 The Layout and Post-Layout Simulation Results..57
Chapter 5 Conclusions……….…...….…....….………61
References……….…………………………….......…….63

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