參考文獻
[1]M. D. Ercegovac and T. Lang, “Division and Square Root - Digit-Recurrence Algorithms and Implementations,” Reading: Kluwer Academic Publisher, 1994.
[2]K. Hwang, “Computer Arithmetic: principles, architecture, and design,” Reading: John Wiley & Son, 1979.
[3]S. F. Oberman and M. J. Flynn, “Design Issues in Division and Other Floating-Point Operations,” IEEE Trans. Computers, vol. 46, no. 2, pp. 154-161, Feb. 1997.
[4]P. Soderquist and M. Lesser, “Division and Square Root - Choosing the Right Implementation,” IEEE Micro, pp. 56-66, July/August 1997.
[5]S. F. Oberman and M. J. Flynn, “Division Algorithms and Implementations,” IEEE Trans. Computers, vol. 46, no. 8, pp. 833-854, Aug. 1997.
[6]J. F. Cavanagh, “Digital Computer Arithmetic: design and implementation,” Reading: McGraw-Hill, 1984.
[7]“IEEE Standard for Binary Floating Point Arithmetic,” ANSI/IEEE Standard 754-1985, New York: IEEE, 1985.
[8]L. Gwennap, “Intel’s P6 Uses Decoupled Superscalar Design – Next Generation of x86 Integrates L2 Cache in Package with CPU,” Microprocessor Report, vol. 9, no. 2, Feb. 1995.
[9]M. D. Ercegovac and T. Lang, “On-the-Fly Conversion of Redundant into Conventional Representations,” IEEE Trans. Computers, vol. 36, no. 7, pp. 895-897, July 1987.
[10]“Pentium Pro Family Developer’s Manual,” Intel, 1996.
[11]“Pentium II Processor Developer’s Manual,’ Intel, Oct. 1997.
[12]“Intel Architecture Software Developer’s Manual,” Intel, Oct. 1997.
[13]“Cyrix M II Data Book,” Cyrix, Apr. 1998.
[14]“Statistical Analysis of Floating Point Flaw in the Pentium(TM) Processor (1994),” Intel Corporation, Nov. 1994.
[15]H.R. Srinivas and K.K. Parhi, “A Fast Radix-4 Division Algorithm and its Architecture,” IEEE Trans. Computers, vol. 44, no. 6, pp. 826-831, June 1995.
[16]J. Cortadella, and T. Lang, “High-Radix Division and Square-Root with Speculation,” IEEE Trans. Computers, vol. 43, no. 6, pp. 919-931, Aug. 1994.
[17]M. D. Ercegovac, T. Lang, and P. Montuschi, “Very-High Radix Division with Prescaling and Selection by Rounding,” IEEE Trans. Computers, vol. 43, no. 8, pp. 909-917, Aug. 1994.
[18]D.E. Thomas and P.R. Moorby, “The Verilog Hardware Description Language Third Edition,” Reading: Kluwer Academic Publisher, 1997.
[19]P. Kurup and T. Abbasi, “Logic Synthesis Using Synopsys Second Edition,” Reading: Kluwer Academic Publisher, 1997.
[20]M. D. Ercegovac, and T. Lang, “Simple radix-4 division with operands scaling,” IEEE Trans. Computers, vol. 39, no. 9, pp. 1204-1208, Sep. 1990.
[21]P. Montuschi, and L. Ciminiera, “Design of a radix 4 division unit with simple selection table,” IEEE Trans. Computers, vol. 41, no. 12, pp. 1606-1611, Dec. 1992.
[22]J. Fandrianto, “Algorithm for high-speed shared radix 4 division and radix 4 square root,” Proc. 8th IEEE Symp. on Computer Arithmetic, pp. 73-79, Como, Italy, May 1987.
[23]M. Kuriyama, S. Atrumi, K. Imamiya, Y. Iyama, N. Matzukawa, H. Araki, K. Narita, K. Masuda, and S. Tanaka, “A 16-ns 1-Mb CMOS EPROM,” IEEE. J. of Solid-State Circuits, vol. 25, no. 5, pp. 1141-1146, Oct. 1990.
[24]N. Tomita, N. Obuaki, J. Miyamoto, K. Imamiya, Y. Iyama, S. Mori, Y. Ohshima, N. Arai, Y. Kaneho, E. Sakagami, K. Yoshikawa, and S. Tanaka, “A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique,” IEEE. J. of Solid-State Circuits, vol. 26, no. 11, pp. 1593-1599, Nov. 1991.
[25]H. Nakai, K. Kanazawa, M. Asano, I. Sato, H. Iwahashi, K. Sakai, M. Yahata, S. Tanaka, N. Tozawa, M. Yatabe, and S. Saito, “A 36ns 1Mbit CMOS EPROM with new data sensing technique,” 1990 Symp. On VLSI Circuits, vol. 10-1, pp. 95-96, 1990.
[26]A. Sekiyama, T. Seki, S. Nagai, A. Iwase, N. Suzuki, and M. Hayasaka, “A 1-V operating 256-kb full-CMOS SRAM,” IEEE J. of Solid-state Circuits, vol. 27, no. 5, pp. 776-782, May 1992.
[27]C.-C. Wang, C.-J. Huang, and I.-Y. Chang, “Design and analysis of Radix-8/4/2 64b/32b integer divider using COMPASS Cell library,” VLSI Design, vol. 11, no. 4, pp. 331-338, Dec. 2000.
[28]C.-C. Wang, C.-J. Huang, and G.-C. Lin, “Cell-based implementation of Radix-4/2 64b/32b signed integer divider using COMPASS Cell library,” IEE Proceedings – Computers and Digital Techniques, vol. 147, no. 2, pp. 109-115, March 2000.
[29]林國卿,“64位元前瞻性微處理器之混合多基底整數除法器設計與實作”,中山大學電機工程學系碩士論文,民國八十七年六月。[30]張一言,“混合基底 8/4/2/之64位元除以32位元整數除法器之設計與實作”,中山大學電機工程學系碩士論文,民國八十八年六月。[31]黃振榮,“應用於訊號處理之高速基本算術元件硬體實作”,中山大學電機工程學系博士論文,民國八十九年五月。[32]C.-C. Wang, Y.-H. Hsueh, C.-W. Chen, J.-J. Wang and R. Hu, “A Cost-Effective 8051-based Chinese Voice Dialer for DECT Handsets,” 5th WSES/IEEE Word Multiconference on Circuits, Systems, Communications and Computers 2001, (accepted, no. 572).
[33]C.-C. Wang, P.-M. Lee, J.-J. Wang and C.-J. Hunng, “Design of a Cycle-Efficient 64B/32B Integer Divider Using a Table-Sharing Method,” 8th IEEE International Conference on Electronics, Circuits and Systems 2001 (ICECS 2001), (accepted, no. 80).