臺灣博碩士論文加值系統

在深次微米的積體電路設計，對於整個晶片的效能，連線的延遲已經變成最主要的關鍵因素。連線的放大（wire sizing），緩衝器的插入（buffer insertion）和裝置的放大（device sizing）是有效的改良延遲的技術，之中緩衝器的插入更是非常有效的技術。隨著半導體技術加倍成長，在晶片中會有很多的緩衝器會被插入，所以一個有系統的緩衝器配置法是需要的。在這篇論文裡，在區塊佈局上，我們會對全域繞線（global routing）和緩衝器插入提出一個有效的演算法。首先一開始的繞線會考量擁擠度和緩衝器的需求，接著藉著繞線情形和時間的需求，緩衝器區塊（buffer block）將會逐漸收集出來。實驗結果證明我們的演算法是快速而且有效的，而且我們完成了百分之百的繞線。

For deep submicron VLSI technology designs,
interconnect delay has become the critical major factor for the circuit performance in VLSI systems.
Wire sizing, buffer insertion and driver sizing are the most effective techniques to improve the interconnect delay.
Among them, buffer insertion particularly is a very effective and powerful method.
With the rapid growth of the IC technology, it is expected that a single chip may have many buffers inserted.
Hence, a systematic buffer planning method is needed.
In this thesis, we will propose an efficient algorithm for global routing and buffer insertion in building block layout.
First, initial routes of all nets are performed taken the congestions and distance into consideration.
Based on the initial routing and timing requirements of all nets, buffer blocks are allocated gradually.
Experimental results show that our algorithm is very fast and efficient and needs less area overhead as compared to [6] . Moreover, our algorithm guarantees 100% nets routing completion.

Introduction
Preliminaries
Delay Model
Problem Formulation
Ket Parameters
Free Space Model
Integrating Global Routing and Buffre Insertion
Properties of Buffer Insertion
Phase1 Routing and Free Space Definition
Phase2 Interconnect Driven Buffer Insertion
Experimental Results
Conclusions

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