臺灣博碩士論文加值系統

在本實驗中，我們利用射頻磁控濺鍍法製作不同結構的鈦酸鍶鋇(BST)薄膜電容器及場效電晶體，在實驗的製程條件下，成長厚度為45nm到200nm的薄膜，探討其基本電性及深入的漏電流機制，並約略估算BST與Si介面間所衍生的SiO2厚度，也對電晶體作基本電性的量測，以及利用閘極二極體量測方式對於氧化鉭電晶體做研究。
在基本電性量測方面，BST薄膜在經過XRD分析後，確定薄膜具有鈣鈦礦結構的成相，膜厚為140nm的MIS電容器經過C-V量測在100kHz下，介電常數值約有70∼80，漏電流密度在1.5V時只有2.11×10-7A/cm2左右，符合未來記憶體應用的需求。考慮製程條件，為了補償氧缺陷，我們在濺鍍過程中通以氧氣，BST與Si介面間有SiO2生成，經計算的結果，等效SiO2的厚度約有5nm；另外有文獻指出Si和BST易有互相擴散的現象，這也會造成造成SiO2的厚度增加。
在漏電流機制的探討方面，MIS電容器在我們所量測的溫度範圍內，在室溫時幾可確定為由普爾法蘭克電流所主導，隨著溫度提高，在我們量測的溫度範圍內，雖然未能確定在溫度升高時是否為普爾法蘭克電流所主導，但由其動態介電常數仍接近合理的理論值範圍，所以普爾法蘭克效應仍是比較明顯的。
其電性上的表現如：由Ids-Vds，Ids-Vgs等圖，可以發現臨界電壓約是0.79V∼1V，次臨界斜率是136.7 mV/dec.和電子遷移率約為206 cm2/V sec，已具有MOSFET的基本效能。我們也利用閘極二極體量測方式對於BST電晶體做研究，發現在BST跟矽介面所量測的介面缺陷電荷，表面復合速率以及通道少數載子等參數，跟傳統的二氧化矽電晶體比較的話，發覺表面特性BST跟矽基板的介面特性比二氧化矽的差。所以仍有許多進步的空間。

In this work , the electrical characteristics of Au/BST/Silicon(P-type) (MIS) capacitors and n-channel metal gate metal-oxide-semiconductor field effect transistors (MOSFET) with (BaxSr1-x)TiO3(BST) gate dielectric are investigated. The BST thin films are deposited by magnetron control RF sputtering. The perovskite phase was confirmed by X-Ray Diffraction spectra. The dielectric constant of 140nm thick BST thin film is around 70~80 at 100kHz and decreases with increasing frequency. The leakage current is around 10-7 A/cm2 in the range of 0~3 V and increases rapidly with increasing temperature. The I-V and C-V characteristics of MIS capacitors are discussed.
The conduction current mechanism of BST films at different temperatures is studied. For MIS structure, Poole-Frenkel is dominant in the room temperature, when the device is negative biased (operated in accumulation region).
The IDS-VDS and IDS—VGS characteristics are measured from MOSFET with BST gate dielectric. The electron mobility obtained from gm versus VG plot was about 206 cm2/V·s. The subthreshold swing was 136.7 mV/dec. The interface density, surface recombination velocity and the minority carrier lifetime measured from gated diodes. Comparison with conventional MOSFETs with SiO2 gate oxide was made.

第一章 緒論
1.1深次微米積體電路技術概況
1.2鐵電材料鈦酸鍶鋇簡介
1.2.1 BST簡介
1.2.2 BST薄膜應用主要有兩大方面
1-3論文重點
1.4鈦酸鍶鋇電容器在未來應用上可能遭遇的問題
1.4.1 漏電流的影響
1.4.2 依時性介電崩潰
1.4.3 氧化層陷阱電荷
1.4.4 尺寸效應
第二章 元件製作流程
2.1 BST薄膜電容器的製備
2.1.1基板及下電極的製作
2.1.2 BST薄膜的成長
2.1.3上電極的製作
2.2電晶體製作流程
2.1.1設備與製作
第三章 薄膜基本電性分析
3.1 X-ray繞射分析
3.2 I-V (電流-電壓)特性曲線量測
3.2.1 MIS結構正負偏壓下的電流特性
3.3.2崩潰電場特性
3.2.3極化電流特性
3.3 C-V(電容-電壓)特性曲線量測
3.3.1相對介電常數
3.4.2介電特性
第四章 漏電流機制探討與溫度效應
4.1電流傳導機制簡介
4.1.1蕭基發射
4.1.2普爾-法蘭克效應
4.1.3室溫下MIS電容器電流對電壓特性量測分析
4.2溫度效應
4.2.1 MIS電容器變溫時I-V特性量測分析
第五章 元件基本電性量測
5.1Ids-Vds Curve的特性
5.2臨界電壓
5.3探討Ids-Vgs Curve的特性
5.4次臨界斜率
5.5遷移率的探討
5.6漏電流機制
5.7基板效應
5.8閘控二極體(gated-diode)量測
5.8.1閘控二極體量測方法與介紹
5.8.2閘控二極體量測理論跟線路接法
5.8.2 (a)量測理論
5.8.2 (b)量測接法
5.8.3閘控二極體量測結果探討
5.8.3 (a)表面復合速率和介面缺陷電荷密度
5.8.3 (b)BST跟Si介面少數載子生命週期
5.8.4閘控二極體量測結論
第六章 結論
附錄
Reference
APPENDIX A - Mask Graph
MOSFET製程參數表

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