臺灣博碩士論文加值系統

近幾年來，利用可重複使用核心（reusable core）或是智慧產權核心（Intellectual Property core）的電路設計流程由於可大幅縮短新晶片產品的上市時間（time-to-market），因此愈來愈受晶片設計者的歡迎。但是由於這些內嵌在系統晶片（SOC）中的核心的輸出入埠並非都被直接連接到晶片上的接腳，因此我們需要可以存取這些輸出入埠的機制（mechanism）。此外，為了避免在晶片測試的開發上耗費太多時間，使得上述設計流程的優點被抵銷掉，因此先前為各個核心所準備的測試向量（Test Pattern）的重複利用變得越來越重要。
在這份論文中，針對系統晶片的測試提出了一個階層式的測試存取架構，這個架構可適用於P1500，IEEE 1149.1及階層式(Hierarchical)的核心。根據測試的核心數目，它的架構可以很有彈性的調整。經由測試介面控制器（Test Interface Controller），可以直接從晶片的接腳存取到內嵌核心的輸出入埠，因此對於測試向量的重複使用可以很容易的達到。
這份論文亦提出系統晶片測試開發的自動化流程及相關的輔助軟體。經由軟體的輔助，核心使用者可以很容易的完成晶片測試的開發工作，包括(1)測試介面控制器及P1500 Wrapper電路產生流程，(2)P1500相容測試向量的轉換流程，(3)系統晶片測試向量的整合流程。
在論文的最後一章，利用一些ISCAS Benchmark電路當作核心組成了測試電路，其中包含有P1500, IEEE 1149.1及階層式的核心。根據實驗的結果，可以發現測試介面控制器額外增加的面積很小。至於採用這個架構額外增加的測試時間，在實驗結果中也可以發現很小，甚至可以被忽略。

In recent years, using reusable cores, i.e., pre-design Intellectual Property (IP) blocks, to shorten the time-to-market for new ICs has become the most popular design methodology. In order to prevent test development from becoming the bottleneck in the entire design flow, the use of the pre-computed test patterns for the embedded cores is necessary.
In this thesis, we propose a hierarchical test access architecture and an automatic test development flow. The proposed architecture is compliant with P1500, JTAG and hierarchical cores. By using the proposed Test Interface Controller, the cores which are deeply embedded into system or
other hierarchical cores can be accessed through the test pins, and the use of the pre-computed test patterns becomes a very easy work. The proposed automatic test development flow cludes the Test Circuit Generation Flow, P1500 Compliant Test Pattern Translation Flow and Test Pattern Integration Flow. For these flows, we also develop some softwares to facilitate the test development procedure to shorten the development time cost.
We also utilize some ISCAS benchmark circuits to implement a experimental circuit. Based on experimental results, we can find that both the area overhead of the Test Interface Controller and the effective test time overhead are small.

1 Introduction 1
1.1 Problem Statement
1.2 IEEE P1500 Spirit
1.3 Introduction of the Proposed Approach
1.4 Thesis Organization
2 PriorWorks 7
2.1 IEEE P1500 Standard for Embedded Core Test
2.1.1 IEEE P1500 Working Group
2.1.2 Dual ComplianceConcept
2.1.3 Scalable Architecture
2.1.3.1 IEEE P1500 Wrapper
2.1.3.2 WIR Instruction
2.1.4 Core Test Language
2.2 Other Related Researches
3 The Proposed Approach 20
3.1 Overview
3.2 Function and Implementation of Each Component
3.2.1 Test Interface Controller (TIC)
3.2.1.1 Finite State Machine (FSM)
3.2.1.2 Configuration Register (CREG)
3.2.1.3 Switch Block(SB)
3.2.1.4 Gating Logic (GL)
3.2.2 P1500 Wrapper
3.2.2.1 Wrapper Instruction Register (WIR)
3.2.2.2 Wrapper Boundary Register (WBR)
3.2.2.3 Wrapper Bypass Register (WBY)
3.2.3 Test Bus
3.3 Automatic Test Development Flow
3.3.1 Test Circuit Generation
3.3.2 Test Pattern Translation
3.3.3 Test Pattern Integration
4 Experimental Result
4.1 Experimental Environment Setup
4.2 Discussion
4.2.1 Area Overhead
4.2.2 Test Time Overhead
5 Conclusions

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