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研究生:鄧光鎧
研究生(外文):Guang-Kaai Dehng
論文名稱:互補式金氧半延遲鎖定迴路及鎖相迴路之實現與應用
論文名稱(外文):Implementation and Application of CMOS DLL/PLL
指導教授:劉深淵
指導教授(外文):Shen-Iuan Liu
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:英文
論文頁數:136
中文關鍵詞:延遲鎖定迴路鎖相迴路積體電路頻率合成器
外文關鍵詞:DLLPLLICFrequency Synthesizer
相關次數:
  • 被引用被引用:2
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  • 下載下載:251
  • 收藏至我的研究室書目清單書目收藏:3
近二十年來,隨著互補式金氧半製程快速而持續的進展,電子系統已朝高度整合與高速操作的方向發展。此時,不同系統之間的同步問題也隨之衍生而出。延遲鎖定迴路與鎖相迴路已被廣泛地應用在同步問題的處理,而本論文主要是探討這兩種迴路的實現與應用。
在第二章,我們提出了一個新式的巢狀式延遲鎖定迴路。它採用一種有別於傳統的巢狀式結構。透過這樣的方式,傳統的一階延遲鎖定迴路可以變成二階系統,而輸出時脈抖動的抑制能力亦隨之提升。此外,我們也引進了一種稱為動態頻寬調整的技巧,用來同時保有比較短的鎖定時間而不影響輸出的時脈抖動表現。我們所提出的巢狀式延遲鎖定迴路是以0.35-微米的互補式金氧半製程製造,電路面積為350  120平方微米。當輸入時脈頻率為125MHz而操作電壓為3.3V時,量測到的方均根抖動及峰值抖動分別是2.213ps和17.4ps。晶片的功率消耗為35mW,其中包括了所有消耗在數位輸出電路的部分。
在第三章,我們提出了一個具有快速鎖定功能的混合式延遲鎖定迴路。在這個混合式延遲鎖定迴路中,數位的部分採用一種二位元連續近似的演算法來縮短鎖定時間,而類比的部分則是用來減少數位部分所產生的殘餘相位誤差。我們所提出的混合式延遲鎖定迴路是以0.25-微米的互補式金氧半製程製造,電路面積為1100  670平方微米。當輸入時脈頻率為100MHz時,量測到的方均根抖動、峰值抖動及靜態相位誤差分別是6.6ps、47ps和12.4ps。當電路鎖定時,功率消耗為15.8mW而操作電壓為2.7V。當殘餘相位誤差小於一個最低位元時,最長的鎖定時間需要13.5個時脈週期。
在第四章,我們提出了一個以0.35-微米互補式金氧半製程製造的低壓鎖相迴路式頻路合成器。透過一組內建在晶片中的倍壓電路,使它可以操作在1V的供應電壓。當我們採用內建在晶片中的電感電容槽式壓控震盪器時,量測到的相位雜訊在1MHz的頻率偏移為-100dBc/Hz,中心頻率為537.6MHz而功率消耗則是15mW,其中壓控震盪器消耗了12mW。另外,當我們採用非內建在晶片中的高性能壓控震盪器時,量測到的相位雜訊在100kHz的頻率偏移為-112.7dBc/Hz,中心頻率為900MHz而功率消耗為3.56mW(不包括壓控震盪器消耗的部分)。此外,倍壓電路的功率效率為77.8%。
.
在第五章,我們討論了延遲鎖定迴路在高速串列傳輸的應用。在這一章,我們提出了一個追蹤式時脈回復接收電路,它可適用於長4.5m的IEEE P1394a高性能串列匯流排。這個接收電路採用一種過取樣的技巧以及數位式的移相方式,用以避免傳統追蹤式接收電路的亞穩態問題,並提高雜訊免疫能力。此外,循環式的相位調整機制也使這個接收電路的操作不會受到資料與時脈通道間信號誤差的影響。我們所提出的追蹤式接收電路是以0.25-微米的互補式金氧半製程製造,電路面積為740  1850平方微米。當操作電壓為2.5伏特時,量測到的最高傳輸速度為800Mb/s,功率消耗為85mW。
The rapid and continuous advances of CMOS processes over the past twenty years have led to a highly-integrated level and a fast operation speed in electronic systems. Meanwhile, the issue of synchronization associated with these systems arises and it is often dealt with by delay-locked loops (DLLs) and phase-locked loops (PLLs). This thesis is mainly dedicated to the implementation and application of CMOS DLLs and PLLs.
In chapter 2, a novel DLL (NDLL) is presented. It adopts a proposed nested topology, which is different from the conventional one. In this way, the NDLL becomes a 2nd-order system, which improves the jitter suppression capability compared to the conventional 1st-order DLL. Besides, a technique called dynamic bandwidth-adjusting scheme (DBAS) is also introduced. It is an efficient strategy to preserve shorter lock time without compromising with the output jitter performance. The proposed NDLL has been fabricated in a 0.35-µm CMOS process and the active area occupies 350  120m2. When the input clock is 125MHz and the supply voltage is 3.3V, the measured rms and peak-to-peak jitters are 17.4ps and 2.213ps respectively. The power consumption is 35mw including the portion consumed by the digital output pads within the chip.
In chapter 3, a fast-lock mixed-mode DLL (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time, while the analog part helps to reduce the residue phase error introduced by the digital part and improve the output jitter performance. The proposed MMDLL has been fabricated in a 0.25-µm CMOS process. It occupies 1100 ×670µm2. The measured rms and peak-to-peak jitters and static phase error are 6.6ps, 47ps and 12.4ps, respectively for a 100MHz input clock. The power consumption is 15.8mW in the locked state at a 2.7V supply voltage. The maximum lock time is 13.5 clock cycles (135ns) when the residue phase error is within 1 LSB (156ps).
In chapter 4, a low-voltage PLL-based frequency synthesizer designed in a 0.35µm CMOS process is presented. It can operate at a 1V supply voltage by means of an on-chip voltage doubler. With an on-chip LC-tank voltage-controlled oscillator (VCO), the measured phase noise at a 1MHz frequency offset from 537.6MHz is -100dBc/Hz and the power consumption is 15mW, where 12mW is consumed by the VCO. With an off-chip high-performance VCO, the measured phase noise is -112.7dBc/Hz at a 100kHz offset from 900MHz and it dissipates 3.56mW (not including VCO). The power efficiency of the on-chip voltage doubler is 77.8%.
In chapter 5, the application of DLLs in high-speed serial links is addressed. A tracking clock recovery receiver for the 4.5meter IEEE P1394a high performance serial bus is presented in this chapter. The proposed tracking receiver utilizes an oversampling technique to avoid the metastable problem and a digital phase shifting approach to improve the noise immunity, compared to the analog one. The cyclic phase adjusting mechanism makes the operation the receiver independent of the intrinsic timing skew between clock and data channels. The proposed tracking receiver has been fabricated in a 0.25-µm CMOS process. It occupies 740 ×1850 µm2. The measured maximum data rate is 800Mb/s and it dissipates 85mW from a 2.5V supply voltage.
Cover
Abstract
Contents
Chapter 1 Introduction to DLLs and PLLs
1.1 Delay-Locked Loops
1.2 Phase-Locked Loops
1.3 Thesis Organization
Chapter 2 A Low-Jitter DLL Using A Nested Topology
2.1 Introduction
2.2 Discrete Z-Domain Analysis of DLLs
2.3 Proposed Nested DLL
2.4 Circuit Description
2.5 Experimental Results
2.6 Summary
Chapter 3 A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm
3.1 Introduction
3.2 Conventional Analog and Digital DLLs
3.3 ADCs vs. DDLLs and the Proposed MMDLL
3.4 Circuit Description
3.5 Experimental Results
3.6 Summary
Chapter 4 A Low-Voltage PLL-Based Frequency Synthesizer
4.1 Introduction
4.2 The Strategies for Low-Voltage Operations
4.3 Low-Voltage PLL-Based Frequency Synthesizer
4.4 Circuit Description
4.5 Experimental Results
4.6 Summary
Chapter 5 A CMOS Tracking Clock Recovery Receiver
5.1 Introduction
5.2 Background
5.3 Proposed Tracking Clock Recovery Receiver
5.4 Circuit Description
5.5 Experimental Results
5.6 Summary
Chapter 6 Conclusion
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(http://cmosedu.com/jbaker/projects/sbfd.htm)
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