臺灣博碩士論文加值系統

在本論文中，我們提出了許多根據MAGFET磁感測器元件設計的磁場到數位轉換器，我們已成功地把磁場訊號分別轉移到頻率、時間和電壓量。這些應用電路已用UMC 0.5mm DPDM CMOS製程及日本SHARP公司0.35mm DPDM CMOS製程實作完成。
在第二章“double MOSFET method”被應用來實現磁場放大器中的線性電阻，使得實現全積體化的磁場感測器界面電路的可能性大增。
在第三章中提出了一個磁控環形振盪器。特別的是，它擁有目前磁控振盪器感測器中最高的靈敏度對功率比。另一個磁場到玻寬數位轉換器也已實現。它可達到非常小的等效解析度，同時，透過離線校正，抵補電壓及增益誤差可進一步被壓制。把磁場轉移到頻域與時域可替感測器系統未來的低電壓操作鋪路。
第四章中，我們把一階磁場到數位轉換器中的磁場放大器與調變器中的積分器結合，可達到節省功率與面積的目的，因為可省掉一個放大器。結合此方法與”虛擬二通路”技巧，我們提出了一個非常精簡，只須一個放大器的二階磁場到數位轉換器，適用於低價位的應用。
在第五章，MAGFET抵補電壓抵消技巧與雙取樣積分分別被應用於磁場放大器與積分器，我們也因此達到了減低抵補電壓與加強增益的目的。
總而言之，我們展示了超取樣(由其是三角積分調變器與漸進式類比數位轉換器)對實現有彈性的、強健的、性能優的感測器界面電路的潛力。根據量測結果，我們證實了所設計電路的正確性與可行性。所提出的這些磁場到數位轉換器具有應用在低價位市場的潛力。

In this thesis, we have proposed several magnetic to digital converters designed with MAGFET, and we have successfully transferred the magnetic signal into frequency domain, time domain, and voltage domain respectively. These application circuits are implemented in UMC 0.5mm DPDM CMOS process and SHARP 0.35mm DPDM CMOS process.
In chapter2, the “double MOSFET method” has been applied to implement the linear resistor pairs in MOP, and this gives the possibility of implementing a fully integrated magnetic sensor interface.
In chapter3, a magnetically controlled ring oscillator has been proposed. In particular, it exhibits the highest sensitivity/power ratio reported to date for a silicon magnetic field sensor based on oscillator. Another magnetic to pulse width digitizer has also been realized, which can reach a very small equivalent resolution. After off-line calibration, the offset can be reduced and gain error can be further minimized. Transferring the magnetic signal to frequency and time domain pave the way for the low voltage operation in the future.
In chapter 4, We combined the MOP with the integrator of the modulator in the first order MDC, thus saving power and area because one opamp is spared. Combining this method with the pseudo two path technique, we presented a very compact second order MDC system using only opamp for low cost applications.
In chapter5, the MAGFET offset canceling technique and differencing sampling technique are applied along with the design of MOP and integrator. The goal of reduced offset and gain factor enhancement are achieved.
To sum up, we demonstrated the potential of oversampling techniques (in particular sigma-delta modulators and incremental A/D converters) for implementing very flexible, robust and performant sensor interface circuits.
The measurement results have verified the correctness and feasibility of designed circuits. Such MDCs have the potential for low cost magnetic sensor applications.

Table of Contents
Chapter 1 Introduction…..………………….……………………..1
1-1 Motivation. 1
1-2 Outline 3
Chapter 2MAGFET Device and MOP 5
2-1 The Hall Effect 5
2-2 MAGFET7
2-2-1 MAGFET Operation7
2-2-2 MAGFET Readout Circuit 8
2-2-3 SPICE Model of the MAGFET9
2-2-4 How to Get Optimum Sensitivity in MAGFET 10
2-3 Fully Differential Magneto-OP11
2-3-1 Concept of a Magneto-OP11
2-3-2 Principle of MOP Operation12
2-3-3 Simulation and Experimental Results14
2-3-4 Summary16
2-4 Resistor Integration17
2-4-1 Experimental Result20
Chapter3 Frequency and Time Domain Magnetic-to-Digital Converters23
3-1 Linear Current Controlled Delay Element23
3-2 Magnetically Controlled Ring Oscillator26
3-3 Single-Ended Two Stage OP28
3-4 Experimental Results29
3-4-1 Summary32
3-5 Magnetic-to-Pulse Signal Generator33
3-5-1 Basic Concepts of Pulse Width Modulation33
3-5-2 Principles of Operation34
3-6 Pulse Shrinking Time-to-Digital Converter36
3-6-1 Basic Concept of Time-to-Digital Converter 36
3-6-2 Realized Time-to-Digital Converter38
3-7 System Structure of Magnetic-to-Digital Converter40
3-7-1 Sign Circuit40
3-7-2 Calibration41
3-7-3 Simulation Results42
3-7-4 Experimental Results43
3-7-5 Summary47
Chapter4 CMOS Oversampling Magnetic-to-Digital Converters49
4-1 Oversampling49
4-2 Noise Shaping51
4-2-1 One Bit DAC52
4-3 Oversampling Analog-to-Digital Converters52
4-3-1 First Order Delta Sigma Modulator53
4-3-2 Second Order Delta Sigma Modulator55
4-3-3 Comparison of First Order and Second Order Modulators55
4-3-4 Delta Sigma Example56
4-4 Magnetically Controlled Current Multiplier ADC57
4-4-1 Magnetically Controlled Current Multiplier57
4-4-2 Continuous Time First Order Delta Sigma Modulator59
4-4-3 Single-ended Opamp of Integrator 61
4-4-4 Magnetically Controlled Current Multiplier ADC62
4-4-5 Experimental Results62
4-4-6 Summary 66
4-5 First Order One Opamp Magnetic-to-Digital Converter67
4-5-1 System Level of MDC67
4-5-2 Linear Resistance Transmission Gate70
4-5-3 Operational Amplifier of Integrator 71
4-5-4 Comparator71
4-5-5 Clock Generator72
4-5-6 Simulation and Experimental Results 73
4-5-7 Summary77
4-6 Second Order 2OP MDC Using Pseudo-2 Path78
4-6-1 System Level of MDC80
4-6-2 Clock Generator 81
4-7 Second Order 1OP MDC Using Pseudo-2 Path81
4-7-1 System Level of MDC81
4-7-2 Experimental Results 82
4-8 Summary85
Chapter5 MDC with Feed-forward Residue Compensation87
5-1 Pattern Noise87
5-2 First Order Feed-forward Residue Compensation88
5-2-1 Principle of First Order FRC88
5-2-2 Integrator Structure90
5-2-3 Two Stage OP Structure91
5-2-4 9 Levels Flash ADC93
5-2-5 15 Bits Up-Down Counter and Control Circuit95
5-2-6 Clock Generator96
5-3 Second Order Feed-forward Residue Compensation97
5-3-1 Principle of Second Order FRC97
5-4 MAGFET Offset Cancellation99
5-5 Experimental Results101
5-5-1 Summary105
Chapter6 Conclusions107
6-1 Conclusions and Contributions107
6-2 Recommendations for Future Research108
Appendix A111
Reference113

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