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研究生:曾博志
研究生(外文):Po-Chih Tseng
論文名稱:具有形狀適應能力可重新組態離散餘弦轉換處理器之設計與實現
論文名稱(外文):Design and Implementation of Reconfigurable Discrete Cosine Transform Processor with Shape-Adaptive Capability
指導教授:陳良基陳良基引用關係
指導教授(外文):Liang-Gee Chen
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:英文
論文頁數:87
中文關鍵詞:可重新組態離散餘弦轉換形狀適應可重新組態運算系統晶片實現視訊編碼
外文關鍵詞:ReconfigurableDiscrete Cosine TransformShape-AdaptiveReconfigurable Computing SystemChip ImplementationFPGA ImplementationMPEG-4Video Coding
相關次數:
  • 被引用被引用:0
  • 點閱點閱:182
  • 評分評分:
  • 下載下載:16
  • 收藏至我的研究室書目清單書目收藏:1
本論文提出了一個具有形狀適應能力之可重新組態離散餘弦轉換處理器,適用於以離散餘弦轉換為基礎的視訊編碼應用。可重新組態離散餘弦轉換處理器結合了一個一般用途的嵌入式處理器系統與一個具有離散餘弦轉換運算加速功能之特殊用途可重新組態附屬處理器。此一附屬處理器可以執行標準的二維8 x 8正反離散餘弦轉換以及較為複雜的形狀適應離散餘弦轉換之正反轉換。由於同時整合了硬體與軟體於此可重新組態離散餘弦轉換處理器之上,此一可重新組態運算系統可以較有彈性的方式執行所有以離散餘弦轉換為基礎的視訊編碼應用,包含了傳統以畫面為基礎的視訊編碼以及最新多媒體應用中的任意形狀視訊物件編碼。
我們使用標準單元式設計流程實現兩個附屬處理器的晶片設計。其一是僅有核心的設計,另一則是為了要實際下線製作之含有可測試性設計考量的設計。可重新組態離散餘弦轉換處理器的整個系統亦經過了以Nios SOPC平台為基礎的FPGA驗證。
我們所提出的系統架構可以視為一個基本的平台,其他功能的附屬處理器都可以被整合在此一系統架構之上。

In this thesis, a Reconfigurable Discrete Cosine Transform Processor with shape-adaptive capability for DCT-based video coding applications is presented. The Reconfigurable DCT Processor incorporates a general-purpose embedded processor system and an application-specific reconfigurable co-processor with DCT computation acceleration. The application-specific reconfigurable co-processor, which is called the Reconfigurable Discrete Cosine Transform Co-Processor, is a reconfigurable architecture that can perform standard 2-D 8 8 DCT/IDCT and both forward and inverse transforms of the more complex SA-DCT. Due to the integration of both hardware and software on Reconfigurable DCT Processor, this reconfigurable computing system can perform all DCT-based video coding applications including traditional frame-based video coding and arbitrarily shaped video objects coding of emerging multimedia applications in a more flexible fashion.
Two chip designs of Reconfigurable DCT Co-Processor are implemented using cell-based design flow. One is the core only design, and the other is the core with DFT consideration design for fabrication. The whole system of Reconfigurable DCT Processor is also verified by FPGA implementation based on Nios SOPC platform.
The proposed system architecture can be regarded as a basic platform, and different co-processors targeting functions other than DCT computation are also possible to be integrated into this system architecture.

1 Introduction ……………………………………………………………1
1.1 Trends of Multimedia Applications ……………………………1
1.2 Evolution of Video Coding Schemes ……………………………2
1.3 Reconfigurable Computing ………………………………………5
1.4 Thesis Organization ………………………………………………6
2 Shape-Adaptive Discrete Cosine Transform ………………………7
2.1 Texture Coding of Arbitrarily Shaped Video Objects in
MPEG-4 ………………………………………………………………7
2.1.1 Coding of Object Blocks …………………………………… 10
2.1.2 Coding of Boundary Blocks ………………………………… 10
2.2 Standard Discrete Cosine Transform ………………………… 11
2.3 Low-Pass Extrapolation Padding Technique ………………… 13
2.4 Shape-Adaptive Discrete Cosine Transform ………………… 14
2.4.1 SA-DCT Forward Transform ………………………………… 15
2.4.2 SA-DCT Inverse Transform ………………………………… 17
3 Algorithm Optimizations and Architecture Implementations
for Discrete Cosine Transform …………………………………… 19
3.1 Algorithm Optimizations for Standard DCT ………………… 19
3.1.1 1-D DCT/IDCT Transform …………………………………… 20
3.1.2 2-D Transform ………………………………………………… 25
3.2 Architecture Implementations for Standard DCT ………… 26
3.3 Architectures Targeting Shape-Adaptive Transform ……… 26
3.3.1 Time-Recursive Architecture ……………………………… 27
3.3.2 Feedforward Architecture ………………………………… 28
3.3.3 Comments…………………………………………………………… 29
4 Reconfigurable Discrete Cosine Transform Processor with
Shape- Adaptive Capability ……………………………………… 30
4.1 Reconfigurable DCT Processor ………………………………… 30
4.2 Reconfigurable DCT Co-Processor …………………………… 32
4.2.1 Algorithm Analysis ………………………………………… 32
4.2.2 Proposed Reconfigurable DCT Co-Processor
Architecture ………………………………………………… 38
4.3 Architecture Design for Reconfigurable DCT
Co-Processor ……………………………………………………… 41
4.3.1 Shape Formation……………………………………………… 41
4.3.2 Texture Processing…………………………………………… 43
4.3.3 Operation Timing of Reconfigurable DCT
Co-Processor ………………………………………………… 58
5 Implementations ……………………………………………………… 60
5.1 Implementation Flow …………………………………………… 60
5.2 Chip Implementations for Reconfigurable DCT
Co-Processor ……………………………………………………… 61
5.2.1 Chip Design Flow …………………………………………… 61
5.2.2 Chip Features and Layout of Core Only Design ……… 64
5.2.3 Design For Testability Consideration ………………… 66
5.2.4 Chip Features and Layout of Core with DFT Design … 68
5.3 FPGA Implementation for Reconfigurable DCT
Processor ………………………………………………………… 70
6 Conclusion …………………………………………………………… 72
BIBLIOGRAPHY …………………………………………………………… 73

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