臺灣博碩士論文加值系統

本論文使用部分解離絕緣體上矽互補式金氧半動態臨限電壓技術提出了兩種適用於低電壓操作具有快速比對能力的內容可定址記憶體記憶單元。
在第二章中提出使用部分解離絕緣體上矽互補式金氧半動態臨界電壓技術擁有快速標籤比對能力之新型低電壓內容可定址記憶體記憶單元，其利用二個通過電晶體去動態控制記憶單元標籤比對部分之電晶體的基體電壓，在操作電壓為0.7伏特下具有快速的標籤比對能力。
第三章中探討部分解離絕緣體上矽元件之浮接基體效應對內容可定址記憶體記憶單元所造成的漏電現象，並提出使用一個二極體接法的P型部分解離絕緣體上矽金氧半元件來動態控制記憶單元讀寫電晶體基體電壓的方法，能有效地解決漏電問題。
在第四章中提出使用部分解離絕緣體上矽互補式金氧半動態臨界電壓技術擁有更快速標籤比對能力之新型低電壓內容可定址記憶體記憶單元，利用離絕緣體上矽技術的優勢來降低記憶單元標籤比對部分電路的最小操作電壓並利用一個輔助電晶體去動態控制標籤比對部分放電電晶體的基體電壓，在操作電壓為0.5伏特至1.2伏特時，其比對延遲時間均較第二章所提新型電路節省44%以上。
以上所提之電路均由二維半導體元件模擬程式MEDICI加以驗證。

This thesis reports two low-voltage Content-Addressable- Memory (CAM) Cells with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques.
In chapter 2, this thesis reports a novel low-voltage Content- Addressable-Memory Cell with a fast tag-compare capability using partially depleted SOI CMOS dynamic-threshold techniques. With two auxiliary pass transistors to dynamically control the bodies of transistors in the tag-compare portion of CAM cell, this SOI CAM cell has a fast tag-compare capability at low supply voltage of 0.7 V.
In chapter 3, this thesis presents the leakage current of the CAM cell due to the floating-body effect of the PD SOI device and reports an approach using a p-type PD SOI MOS device with diode connections to dynamically control the bodies of access transistors of the CAM cell. Using this approach the leakage current can be eliminated effectively.
In chapter 4, this thesis reports a novel low-voltage Content- Addressable-Memory Cell with a faster tag-compare capability using partially depleted SOI CMOS dynamic-threshold techniques. Using the advantage of the SOI techniques to decrease the operation voltage of the tag-compare portion of the CAM cell and using an auxiliary transistor to dynamically control the body of the discharge transistor of the CAM cell, the delay time of tag-compare can be reduced to the 44% delay time of the circuit reported in chapter 2 at 0.5-1.2 V supply voltage.
The above-mentioned circuits are verified by the 2D MEDICI simulation program results.

目錄
第一章導論 ................................................1
1.1 簡介 ...............................................1
1.2 絕緣體上矽金氧半元件 ...............................2
1.3 動態臨界電壓金氧半技術 .............................4
1.4 本論文目標 .........................................6
第二章使用部分解離絕緣體上矽互補式金氧半動態臨界電壓技術具有
新型低電壓內容可定址記憶體記憶單元 ..................6
2.1 簡介 ................................................8
2.2 內容可定址記憶體記憶單元的基本架構 ..................10
2.3 新型低電壓絕緣體上矽內容可定址記憶體記憶單元 ........11
2.4 效能與討論 ..........................................14
2.5 結論 ................................................23
第三章部分解離絕緣體上矽之浮動基體效應在內容可定址記憶體記憶
單元所造成的漏電問題 ............................... 24
3.1 簡介 ................................................24
3.2 部分解離絕緣體上矽之浮動基體效應在內容可定址記憶體記憶
單元的漏電現象 ......................................27
3.3 漏電流問題之解決與討論 ..............................34
3.4 結論 ................................................38
第四章適用於低電壓操作具有更快速標籤比對能力之新型絕緣體上矽
內容可定址記憶體記憶單元 ............................39
4.1 簡介 ................................................39
4.2 傳統九個電晶體的內容可定址記憶體記憶單元 ............40
4.3 新型十一個個電晶體的內容可定址記憶體記憶單元 ........42
4.4 結論 ................................................51
第五章 總結 ..................................................53
參考文獻 .....................................................55

第一章
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第二章
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第三章
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第四章
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