臺灣博碩士論文加值系統

因為容易設計及穩定的特性，延遲鎖定回路(Delay-Locked Loops)已經比鎖相回路(Phase-Locked Loops)更廣泛地使用在時脈誤差校正上。現今，越來越多的應用已經開始使用延遲鎖定回路，例如時脈回復及本地震盪器電路，而這些應用在以前卻只能使用鎖相回路。因此，延遲鎖定回路將日益重要。
這本論文中包含了三顆延遲鎖定回路的設計與實現。首先，一利用數位控制半複製回路達到低時脈抖動(low jitter)的延遲鎖定回路被提出來，其架構是修改文獻[1]中所提出自偏壓延遲鎖定回路，使它同時兼具頻寬追蹤(Bandwidth Tracking)及低時脈抖動的特性，量測的結果將會證明這個論點。
當延遲鎖定回路需寬頻操作時，傳統的延遲鎖定回路就會遭遇鎖定錯誤的問題。因此，在第二部份，一起動控制電路(Startup-Controlled Circuit)將被提出以解決諧波鎖定的問題。透過這項機制，整個電壓控制延遲線(Voltage-Controlled Delay Line )所提供的延遲時間會剛好為一個時脈週期。
最後，根據上一部份所提出的方法，一個更寬頻操作及延遲時間為一時脈週期的延遲鎖定回路被提出。理想上，這顆延遲鎖定回路的操作頻率從1/(N×TDmax)到(1/ TDmin)，其中N代表延遲細胞(DelayCell)的個數、TDmax及TDmin分別代表延遲細胞最大及最小的延遲時間。量測的結果將會顯示這延遲鎖定回路確實具有寬頻操作及延遲時間為一時脈週期的特點。

Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loops (PLLs) because of easy design and inherent stable. Nowadays, more and more applications, such as Timing Recovery and Local Oscillator where only PLL can be used in the past, are also employed DLLs. So, the DLLs will be more significant in the near future.
This work contains three design and realization of DLLs. First, a low jitter DLL using the Digital-Controlled Half Replica Delay Line (DCHRDL) is proposed here to modify the architecture of self-biased DLL presented in [1]. The DCHRDL provides a stable bias voltage to the charge pump for low jitter operation and the feature of bandwidth tracking that proposed by [1] is still kept. Measurement results will prove the point of view.
For wide-range operation, conventional DLL may suffer from locked delay ambiguity. So, in second part, a startup-controlled circuit is proposed for the DLL to fix the problem of harmonic locking. Through this control, the total time delay from all delay stages is precisely one period of the input reference signal.
Finally, a DLL with wide-range operation and fixed latency of one clock cycle is proposed based on the technique presented in the second part. Ideally, the frequency range that the proposed DLL can operate is from 1/(N×TDmax) to 1/TDmin, where N is number of delay cells used in the delay line, TDmin and TDmax are the minimum and maximum delay of unit delay cell, respectively. Measurement results will show the proposed DLL indeed has the feature of wide-range operation and fixed latency of one clock cycle.

Chapter1 Introduction
1.1 Motivation
1.2 Thesis Overview
Chapter2 The Basics of Delay-Locked Loop
2.1 Digital Delay-Locked Loop Overview
2.2 Introduction of Analog Delay-Locked Loop
2.3 The Applications for Delay-Locked Loop
Chapter3 A Low Jitter Delay-Locked Loop Using Digital-
Controlled Half Replica Delay Line (DCHRDL)
3.1 Introduction of Self-Biased Delay-Locked Loop
3.2 Circuit Description of the Proposed Delay-Locked Loop
UsingDCHRDL
3.3 Measurement Results
3.4 Conclusions
Chapter4 A Wide-Range Delay-Locked Loop with Multiphase Outputs
4.1 Range Problem of the Conventional DLLs and its solution
overview
4.2 Proposed Architecture and Circuit Description
4.3 Conclusions
Chapter5 A Delay-Locked Loop with Wide-Range Operation and
Fixed Latency of One Clock Cycle
5.1 System Architecture and Circuits Descriptions
5.2 Measurement Results
5.3 Conclusions
Chapter6 Conclusions and Future Works

[1] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, no 11, pp. 1723-1732, Nov. 1996.
[2] C. H. Kim et al, “A 64-Mbit, 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system”, IEEE J. Solid-State Circuits, vol. 33, no 11, pp. 1703-1710, Nov. 1998.
[3] Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance”, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 377-384, Mar. 2000.
[4] D. J. Foley, and M. P. Flynn, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator”, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 417-423, Mar. 2001.
[5] Y. Okajima, M. Taguchi, M. Yanagawa, K. Nishimura, and O. Hamada, “Digital delay locked loop and design technique for high-speed synchronous interface”, IEICE Trans. Electron., vol. E79-C, pp.798-807, June 1996.
[6] J. U. Wang, “The design and realization of clock synchronizer for high speed digital systems”, MS thesis, National Taiwan University, Department of Electrical Engineering, June 1998
[7] G. K. Dehng, J. M. Hsu, C. Y. Yang, and S. I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop”, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1128-1136, Aug. 2000.
[8] MEAD Microelectronics Inc., “Lecture notes for phase-locked loops, oscillators, and frequency synthesizer”, 1998
[9] R. B. Watson, Jr. and R. B. Iknaian, “Clock buffer chip with multiple target automatic skew compensation”, IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1267-1276, Nov. 1995.
[10] S. I. Liu, J. H. Lee, and H. W. Tsao, “Low-power clock-deskew buffer for high-speed digital circuits”, IEEE J. Solid-State Circuits, vol. 34, no 4, pp. 554-558, Apr. 1999.
[11] H. Sutoh, K. Yamakoshi and M. Ino, “Circuit techniques for skew-free clock distribution”, in IEEE Custom Integrated Circuits Conf., pp. 163-166, 1995.
[12] C. Y. Yang and S. I. Liu, “A one-wire approach for skew compensating clock distribution based on bidirectional techniques”, IEEE J. Solid-State Circuits, vol. 36, no 2, pp. 266-272, Feb. 2001.
[13] M. Galles et al. “Spider: a high-speed network interconnect”, IEEE Micro, J vol.17, no. 1, pp. 34-39, Jan.-Feb. 1997.
[14] John E. McNamara, “Technical Aspects of Data Communication”, 2nd ed., Digital Press, Bedford, MA, 1982.
[15] G. Chien and P. R. Gray, “A 900MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications”, IEEE J. Solid-State Circuits, vol. 35, no 12, pp. 1996-1999, Dec. 2000.
[16] G. Chien, “Low-noise local oscillator design techniques using a DLL-based frequency multiplier for wireless applications”, Ph. D. dissertation, Univ. of California, Berkeley, 2000.
[17] J. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter”, Electronics Letters, vol. 29, pp. 1222-1223, June 1993.
[18] A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters”, Electronics Letters, vol. 32, no.12, pp.1055-1057, June 1996.
[19] K. L. Fong, C. A. T. Salama, “A 10Bit Semi-Algorithmic Current Mode DAC”, IEEE International Symposium on Circuits and System, vol. 2, pp. 978-981, May 1993.
[20] R. E. Best, Phase-locked loops: theory, design and applications, New York: McGraw-Hill, 1998
[21] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110MHz of lock range for microprocessor”, IEEE J. Solid-State Circuits, vol. 27, no 11, pp. 1599-1607, Nov. 1992.
[22] S. Kim, et al., “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL”, IEEE J. Solid-State Circuits, vol. 32, no 5, pp. 691-700, May 1997.
[23] J. G. Maneatis, “ Precise delay generation using coupled oscillator”, Ph. D. dissertation, Stanford Univ., June 1994.
[24] Stefanos Sidiropoulos, “High-Performance Inter-Chip Signalling”, Ph.D. Dissertation, Stanford University, 1998.
[25] Behazad Razavi, Editor, “ Monolithic Phase-Locked Loops and Clock Recovery Circuits”, IEEE Press, 1996.