臺灣博碩士論文加值系統

摘要
本論文主要是研究界面陷阱與氧化層陷阱對極薄氧化層金氧半元件的電流電壓與氧化層崩潰特性之影響。此外，也探討在快速熱氧化與快速熱氧化後退火處理等製程有無受光直接照射加熱對上述特性的影響。
首先研究電壓施加引起界面陷阱電荷造成氧化層位障形狀改變對低電壓穿隧電流影響的效應。我們發現對處於直接穿隧範圍的極薄氧化層而言，它的低電壓穿隧電流是與氧化層位障形狀有著緊密的相關性。實驗觀察經過高電場施加後，在電流電壓曲線中存在著一個不改變的點。當偏壓小於這個點的電壓時，閘極電流隨著加電壓的時間而減少，然而當偏壓大於這個點的電壓時，閘極電流隨著加電壓的時間而增加然後趨於飽和。這所觀察到的現象是無法以傳統的陷阱輔助穿隧傳導機制來解釋，但卻可以用由於氧化層位障形狀變動而改變穿隧機率來說明。於是我們提出一個界面陷阱電荷模型來解釋上述所觀察到的不動點的特性。從這個模型可以發現這不動點所對應的電壓正是加電壓而使半導體費米能階位於中間能隙所需要的偏壓，因此可以從該電壓計算得到初始的氧化層電荷密度。
接著研究以階梯上升及階梯下降的電壓施加方式來檢視從半導體基板注入載子到氧化層的薄氧化層性質。一般而言，從閘極注入會造成毀滅性的介電質崩潰使已損壞的氧化層遭到永久性的破壞，且在電流電壓曲線中是呈現電阻似的行為。然而對基板注入而言卻有三種相異模式存在於電流電壓特性中，分別為電阻形式、磁滯形式、與無崩潰形式等模式。此外，它們的發生頻率是與氧化層厚度相關的。對於薄於2.4奈米的氧化層，由於少數載子的限制，正偏壓下之閘極電流幾近於飽和。對於較厚的氧化層由於在矽表面缺陷的增加使得少數載子產生速率增加，如此一來氧化層可以獲得較大的電場與較多的載子注入，因此造成破壞性的損害，也就是出現電阻形式的模式。對於3奈米的氧化層由於氧化層受到較輕的損害，偶而出現磁滯形式的模式。再者，我們研究了這三種模式與氧化層厚度的相關特性。對研究具有極薄氧化層的元件，這些現象是有其重要性的。
除此之外，在快速熱氧化後退火處理製程中光能量對極薄氧化層閘極注入下之軟崩潰特性之影響亦進行探討。一般閘極注入載子所造成的崩潰是被歸納為硬崩潰與軟崩潰兩種。兩者的產生是與製程及電場有關。於快速熱氧化後退火處理製程中，分別進行於正面與背面接受鹵素光源照射，並比較其樣品特性差異。再者，我們發現正面受光照射的樣品比背面受光照射的容易發生軟崩潰。這些結果顯示光能量不僅增強矽氧鍵結的強度進而抑制崩潰點的側向傳遞，也增強了局部化缺陷進而形成漏電流的傳導路徑。因此瞭解光效應在快速熱氧化後退火處理製程所扮演的角色是有助於控制極薄氧化層的電特性。
然而，對於基板注入載子之崩潰模式，我們發現不論是在快速熱氧化後退火或快速熱氧化製程，正面受光照射的樣品其磁滯崩潰模式的發生機率比背面受光照射的來得高。這是因為基板注入載子的崩潰除了與氧化層特性有關外，基板的缺陷密度不僅會影響少數載子產生速率也改變其崩潰行為，而基板缺陷的分布是會受照光製程而有所影響的。在快速熱氧化後退火處理製程中我們觀察到正面受光照射樣品的閘極飽和電流比背面受光照射的來得大，同時由不同頻率的電容電壓曲線中也發現正面受光照射樣品的少數載子的產生速率比背面受光照射的來得大。這些結果顯現矽基板內的陷阱在照光的製程中是較容易被產生，使得基板注入載子之崩潰行為出現差異。從上面所觀察的現象我們推論在快速熱製程中光能量扮演著一重要的角色，它會影響到金氧半元件結構的特性。

Abstract
The effect of interface and oxide traps on the current-voltage and oxide breakdown characteristics for metal-oxide-semiconductor ( MOS ) structures with ultra-thin gate oxides was studied in this work. In addition, we also investigate the difference of those between the front- and back-side heated samples whether for rapid thermal oxidation ( RTO ) or for rapid thermal post oxidation annealing ( POA ) processing.
The effect of oxide barrier shape change caused by stress-induced interface trap charges on the low-voltage tunneling current ( LVTC ) characteristics of ultra-thin gate oxides ( ~2nm ) is first studied. It was found that for an ultra-thin gate oxide working in the direct tunneling regime, the LVTC behavior is strongly dependent on the barrier shape of the oxide. After high field stress, anomalous LVTC phenomenon is observed. There is an invariant point existing in current-voltage ( I-V ) curves. For a bias smaller than the value of the invariant point, the gate current decreases with stress time. However, for a bias larger than that, the gate current increases with stress time and then saturates. This phenomenon cannot be explained by conventional trap-assisted tunneling conduction, but by the change of tunneling probability due to barrier shape variation. An interface trap charge model is proposed to explain the observed invariant point mentioned above. From this, one can find the voltage corresponding to the midgap bias and, therefore, the initial effective oxide charge number density.
Then, the thin oxide property in an MOS structure subjected to substrate injection from semiconductor into oxide is investigated by means of ramp-up and ramp-down I-V measurements. Generally, the gate injection causes catastrophic dielectric breakdown, and the damaged oxide suffers from permanent destruction which exhibits resistor-like behavior in the I-V curves. For substrate injection, however, there are three distinct modes existing in I-V characteristics. They are resistor-like ( BD-R ), hysteresis-like ( BD-H ), and saturation, i.e., no breakdown ( NBD ). Besides, their occurrence frequencies are dependent on the oxide thickness. For oxides thinner than 2.4nm, in general, the gate current nearly saturates due to the limitation of minority carriers. For 3.9nm oxide, the minority carrier generation rate increases due to the increase in the trap density near Si surface. Thus the oxide sustains higher field and larger carrier injection, so that these cause the destructive damage, i.e., resistor-like mode. For 3nm oxide, sometimes the hysteresis-like mode appears due to light damage in the oxide. Moreover, the related characteristics of these modes are studied and exhibit oxide thickness dependence. These phenomena are important to recent study on devices with ultra-thin gate oxides.
In addition, soft breakdown properties influenced by photon energy during rapid thermal post oxidation annealing ( POA ) for ultra-thin gate oxides are investigated. Generally, under gate injection oxide breakdown can be classified into normal hard breakdown ( HBD ) and soft breakdown ( SBD ). It was found that the occurrence of HBD and SBD depends on the process and stress field. Samples with front- and back-side illuminated by a tungsten halogen lamp during rapid thermal POA were examined. Moreover, we find that the front side illuminated oxides show easier SBD than the back side ones. These results indicate that the photon energy may not only enhance the strength of Si-O bonds to suppress the lateral propagation of breakdown spots, but also localize defects to form a conductive path of the leakage current. The understanding of the photon effect in rapid thermal POA is useful for controlling the electrical properties of ultra-thin gate oxides.
Nevertheless, for the breakdown behavior under substrate injection, it was found that the occurrence frequency of BD-H mode is larger for the front-side heated samples than for the back-side ones whether for RTO processing or for POA one. It is believed that for substrate injection, the oxide breakdown is related to oxide quality and the minority carrier generation rate contributed by defect density in substrate. The distribution of defects can be influenced by the illumination processing. It was also observed that for POA processing, the gate saturation current density is larger for the front-side heated samples than for the back-side ones. From C-V measurements with various frequencies, furthermore, it was observed that the generation rate of minority carriers is larger for the front-side heated samples than for the back-side ones. These results show that Si bulk traps are much easy to be created in the direct illumination processing. From above observation, we conclude that photon energy plays an important role in rapid thermal processing ( RTP ). The characteristics of MOS structures can be influenced by the direct illumination during RTP.

Cover
Abstract ( in Chinese )
Abstract ( in English )
Contents
Table Caption
Figure Captions
Chapter 1 Introduction
Chapter 2 Study on Low-Voltage Tunneling Current ( LVTC ) for Ultra-Thin Gate Oxides after High Field Stress
2.1 Introduction
2.2 Experimental
2.3 Results and Discussion
2.4 Conclusion
Chapter 3 Study on Breakdown Characteristics of Ultra-Thin Gate Oxides (4nm) in MOS Structures Subjected to Substrate Injection
3.1 Introduction
3.2 Experimental
3.3 Results and Discussion
3.4 Conclusion
Chapter 4 Study on Breakdown Properties Influenced by Photon Energy during Rapid Thermal Processing ( RTP ) for Ultra-Thin Gate Oxides
4.1 Introduction
4.2 Experimental
4.3 Results and Discussion
4.4 Conclusion
Chapter 5 Conclusion and Suggestion for Future Work
5.1 Conclusion in This Work
5.2 Suggestion for Future Work
Appendix 1 The Simulation of J-V Curves for MOS Structures
Appendix 2 The Simulation of Temperature Profile on Si Wafer
Appendix 3 List of Abbreviation
References

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