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研究生:蕭俊偉
研究生(外文):Jun-Wei Hsiao
論文名稱:設計最佳平行前置電路
論文名稱(外文):Designing Depth-Size Optimal Parallel Prefix Circuit WE4
指導教授:林彥君林彥君引用關係
指導教授(外文):Yen-Chun Lin
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:34
中文關鍵詞:前置運算前置電路深度-節點數最佳扇出
外文關鍵詞:parallel prefixprefix circuitsdepth-size optimalfan-out
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前置運算就是對n個輸入數值x1, x2,..., xn與具結合性
的二元運算,求得n個前置值x1, x2,..., xi,1≦i≦n.因為
前置運算有很多應用,所以有許多的前置電路被設計出來.任何一個前置電路
D,其深度d(D)與運算節點數s(D)滿足d(D)+s(D)≧2n-2.因此,若d(D)
+s(D)=2n-2,則D為最佳前置電路.前置電路的運算節點個數愈少,則所需
的積體電路面積就愈小;深度愈小,則輸出的速度愈快;節點的扇出愈大,則所需
的積體電路面積會愈大,速度也愈慢.在本論文中,我們建造扇出為4的最佳前置電路WE4.
且深度介於2log n-6與2log n-3之間.在深度的比較上,WE4與扇出為4的最佳前置電路Z4各有小部分比對方多一,
但在大部分的情況,d(WE4)=d(Z4);與已知的其他扇出為4的最佳前置電路相比,WE4的深度是最小的.
由於WE4的扇出比無限扇出的最佳前置電路QL的扇出小得多,所以WE4的積體電路面積較小,
速度也可能比QL快.
Give n values x1, x2,..., xn and an associative binary operation , the prefix
problem is to computex1, x2,..., xi,1≦i≦n. Because prefix computation has
many applications, many combinational circuits for solving the prefix problem, called prefix
circuit, has been designed. The depth d(D) and the size s(D) of an n-input prefix circuit
D satisfy d(D) + s(D) ≧2n - 2; thus, the prefix circuit is depth-size optimal if d(D) +
s(D) = 2n - 2. A prefix circuit with a smaller size requires less VLSI area, and one with
smaller depth is faster. In addition, a node with a greater fan-out is slower and requires
larger VLSI area. In this thesis, we construct a depth-size optimal parallel prefix circuit WE4 with
fan-out 4, the depth of WE4 between 2log n-6 and 2log n-3.Compared with another depth-
size optimal prefix circuit Z4, the depth of WE4 may be less than or greater than that of
Z4. The depth of WE4 is smaller than all the other known prefix circuits with fan-out 4. 
Compared with QL, a depth-size optimal prefix circuit with unbounded fan-out, WE4 may
have may a greater or equal depth than QL; however, because the fan-out of WE4 is smaller than
that of QL, the VLSI area of WE4 is smaller, and WE$ may be faster.
第 1 章   簡介                     1
 1.1. 平行前置電路的介紹          1
 1.2. 相關研究                    3
 1.3. 論文組織                    4
第 2 章   舊有的前置電路及性質             5
 2.1. 分層式前置電路P   5
 2.2. 扇出最多為4的前置電路Q              6
 2.3. 節點數最佳前置電路W             8
 2.4. 前置電路的合成及節點數最佳前置電路的相關性質  8
 2.5. 最佳前置電路Z4及QL的深度   10
第 3 章   扇出為4的最佳前置電路             11
 3.1. 扇出為4的節點數最佳前置電路WL        11
 3.2. 節點數最佳前置電路WV           16
 3.3. 扇出為4的最佳前置電路WE4           21
第 4 章   最佳前置電路的比較              27
第 5 章   結論與未來研究方向              31
 5.1. 結論                   31
 5.2. 未來研究方向                  31
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