MOSFET是微處理器及動態記憶體等ULSI電路的基礎構成元件，過去為了增加積集度並提升電路特性，已有非常多的學者投入研究如何有效降低CMOS元件的大小。然而若僅是單純降低元件的尺寸卻未合理的注意其他製程參數，將會導致各種非理想的電路特性。
在CMOS技術中，不論是對元件設計或電路模擬，通道長度都是非常重要的參數。雖然已經有許多的方法提出要來萃取有效通道長度，其中大部分是以I-V量測為基礎，也有其他少數是以C-V量測為基礎。但是他們都無法有效而準確的萃取元件參數，特別是當元件已進步到0.25 以下或更新的世代之際。
在本論文中，我們將提出一個新修正的C-V量測方法─電容比例量測法（C-R method），根據我們所提出的新方法，可以輕易而有效的決定出有效通道長度 、冶金通道長度 、製程偏差長度 、延伸重疊長度 、源/汲極串聯電阻 、閘/汲極間電容 等元件參數。
同時根據C-R method的演算法，我們發展了一套自動化量測系統來幫助萃取以上這些參數。透過自動化的量測與萃取過程，任何工程師都可以輕易的萃取元件參數並做製程監控。這個系統最大的優點是能夠得到合理而可信的結果，除此之外在未來應用時花費在量測的時間與金錢也將降低。最後，我們也將展示使用這套系統來萃取薄閘極元件參數的容易性與方便性。

The MOSFET is the building block of ULSI circuits in microprocessor and dynamics memories. In order to increase the packing density and to improve circuit performance, many researchers have invested their efforts in scaling down the CMOS device size. However, simply reducing device dimension without paying attention to other processing parameters will cause a variety of non-ideal characteristic.
In CMOS technology, channel length is a key parameter used for device design and circuit simulation. Though many methods have been proposed for the extraction of effective channel length. Most of them are based on I-V measurement and some others are based on C-V measurement. But they are all failed as the generation goes down to quarter micron or beyond.
In this thesis we proposed a new approach for extracting advanced CMOS device parameters by using a modified C-V method, named capacitance-ratio method (C-R method). According to the C-R method, we could determine the effective channel length , metallurgical channel length , process bias , extension overlap bias , source-to-drain series resistance , and the gate to drain capacitance easily.
By the algorithm of C-R method, we want to develop an automatic measurement system to help extracting these parameters. With the help of automatic measurement system, one can easily extract parameters and monitor fabrication process. The greatest worth of the system is able to get reasonable and consistent results, besides the cost and time in measurement will be lower in future application. Finally, We show the ease of using our system to extract thin gate oxide parameter.

Chapter 1 Introduction1
1.1 Preview1
1.2 Research Motivation2
1.3 Design Goals4
1.4 Organization of Thesis5
Chapte 2 Review of Related Works and Discussions6
2.1 Various terms of Channel Lengths6
2.2 Review of I-V Extraction Method8
2.2.1 Channel-Resistance method8
2.2.2 S. S-S Chung’s Method9
2.2.3 Shift and Ratio Method11
2.3 Review of Related C-V Extraction Method13
Chapter 3 Extraction Algorithm of Capacitance-Ratio Method16
3.1 Ideal C-V Characteristics16
3.2 Intrinsic and Extrinsic Capacitance18
3.3 Compensation Factor22
3.4 Extraction of Various Lengths26
3.5 Extraction of Cgd and Rsd28
Chapter 4 System Architecture and Implementation31
4.1 Planning of Experiment31
4.2 Automatic Measurement system32
4.3 HP-IB Interface34
4.4 Software development38
Chapter 5 Experimental Results and Discussions43
5.1 Software Test and Verification43
5.2 Discussions of Device/Process Parameters47
5.3 Comparisons with Other Method48
5.4 Optimization Using C-R method53
Chapter 6 Conclusion and Further Research55
6.1 Conclusion55
6.2 Further Research56
Reference58

[1] K. K. Ng, S. A. Eshraghi and T. D Stanik, “An improved generalized guide for MOSFET scaling,” IEEE Trans. Electron Devices, vol. ED-40, no. 10, p. 1895, Oct. 1993.
[2] J. J. Maa and C. Y. Wu, “A new constant-field scaling theory for MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-42, no. 7, p. 1262, July 1995.
[3] J. G. J. Chern, P. Chang, R. F Motta and N. Godinnho, “A new method to determine MOSFET channel length,” IEEE Electron Device Lett., vol. EDL-1, no.9, p. 170, Sep. 1980.
[4] Steve Shao-Shiun Chung and Jenq-Sheng Lee, “A new approach to determine the drain-and-source series resistance of LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-40, no. 9, p.1709, Sep. 1993.
[5] Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari and G. G. Shahidi, “A new ‘shift and ratio’ method for MOSFET channel-length extraction,” IEEE Electron Device Lett., vol. EDL-13, no. 5, p. 267, May 1992.
[6] Yuan Taur, “MOSFET channel length: extraction and interpretation,” IEEE Trans. Electron Devices, vol. ED-47, no. 1, p. 160, Jan. 2000.
[7] Jyh-Chyurn Guo, Steve Shao-Shiun Chung and Charles Ching-Hsiang Hsu, “A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-41, no. 10, p. 1811, Oct. 1994.
[8] S. W. Lee, “A capacitance-based method for experimental determination of metallurgical channel length of submicron LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-41, no.3, p. 403, Mar. 1994.
[9] X. Liu, J. Kang, and R. Han, “The influence of tunneling effect and inversion layer quantization effect on deep submicron MOSFET,” Solid-State and Integrated Circuit Technology, 1998. Proceeding, p. 432, 1998.
[10] Hans van Meer, “Limitations of Shift-and-Ratio based extraction techniques for MOS transistors with halo or pocket implants,” IEEE Electron Device Lett., vol. EDL-21, no. 3, p. 133, Mar. 2000.
[11] Khaled Ahmed, Indranil De, Carl Osburm, Jimmie Wortman, and John Hauser, “Limitations of the Modified Shift-and-Ratio technique for extraction of the bias dependence of and of LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-47, no.4, p. 891, Apr. 2000.
[12] J. S. Shiu, “The study of thin gate oxide parameter extraction for advanced device by C-V measurement,” Master Thesis, Institute of Mechatronics, National Taipei University of Technology, Taiwan, R.O.C, July, 2000.
[13] HP 4284A Precision LCR Meter Operation Manual. Hewlett-Packard Japan, Ltd., Aug. 1998.
[14] David A. Patterson, John L. Heneessy. Computer organization & design the hardware/software interface, Morgan Kaufman, San Francisco, 2nd edition.
[15] Stephen A. Campbell. The science and engineering of microelectronic fabrication. Oxford University Press, New York, 1996.
[16] Yuan Taur, Tak H. Ning. Fundamentals of modern VLSI devices. Cambridge University Press, New York, 1998.
[17] Donald A. Neamen. Semiconductor physics and devices: basic principles, Irwin, Boston, 1992.
[18] C.Y. Chang, S. M. Sze. ULSI devices. Wiley, New York, 2000.
[19] S. M. Sze. Semiconductor devices, physics and technology. Wiley, New York, 1985.
[20] ISE TCAD manuals Volume 3. ISE Integration System Engineering AG, Release 4.
[21] W. Liu, X. Jin, Kanyu M. Cao, Chenming Hu, “BSIM 4.0 MOSFET model─ User’s manual,” http://www-device.eecs.Berkeley.edu/~bsim3/bsim4.html.
[22] H.S. Huang, J.S. Shiu, S. J. Lin et. al, “A modified C-V method used for the extraction and process monitoring of advanced 0.15 um CMOS device and beyond,” Jpn J. Appl. Phys., 2000, (Ref No. 00R05077)
[23] H.S. Huang, S. J. Lin, Y. J. Chen et. al, “A capacitance ratio method used for the extraction of an advanced MOS device with a halo implant,” Jpn J. Appl. Phys., 2000, (Ref No. 00R09032)