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[1]C. Codella and S. Ogura, IEDM Tech. Digest, pp.230-233, 1985. [2]A. Hori et al., IEDM Tech. Digest, pp.641-644. 1991. [3]K. K. Ng and J. R. Brews, “ Measuring the effective channel length of MOSFET’s,” IEEE Circuits and Devices, p.33, 1990. [4]Terda, K. and Muta, H. “A new method to determine effective MOSFET channel length characterization of LDD MOSFET’s” Jpn. J. Appl. Phys., vol. 18, p.953, 1979. [5]Jiro Ida, Akio Kita and Fumio Ichikawa “A new extraction method for effective channel length on lightly doped drain MOSFET’s” proc. IEEE 1990 Int. Conf. on micro. Test structures, vol. 3, March 1990. [6]Tuar, Y. ”A new shift-and-ratio method for MOSFET channel-length extraction” IEEE Electron Device Letters, vol. 13, p. 267, 1992. [7]Shiuh-Wuu Lee, “A capacitance-based method for experimental determination of metallurgical channel length of submicron LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, no. 3, Mar 1994. [8]Guo, J. C.; Chung, S. S.-S. and Hsu, C. C.-H. “A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET’s,” IEEE Trans. Electron Devices. Vol. 41, p. 1811, Oct. 1994. [9]Hans van Meer, “Limitations of Shift-and-Ratio based extraction techniques for MOS transistors with halo or pocket implants,” IEEE Electron Device Lett., vol. EDL-21, no. 3, p. 133, Mar. 2000. [10]Khaled Ahmed, Indranil De, Carl Osburm, Jimmie Wortman, and John Hauser, “Limitations of the Modified Shift-and-Ratio technique for extraction of the bias dependence of and of LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-47, no.4, p. 891, Apr. 2000. [11]Tuar, Y. “MOSFET channel length: extraction and interpretation” IEEE Trans. Electron Devices. Vol. 47, p. 160, January 2000. [12]James R. Pfiester, Mark E. Law, and Robert W. Dutton, “Improved MOSFET short-channel device using germanium implantation” IEEE Electron Device Letters, vol. 9, no. 7, July 1988. [13]Huang, C. T. Lei, T. F. Chu, C. H. and Shvu, S. H. “The influence of Ge-implantation on the electrical characteristics of the ultra-shallow junction fromed by using silicide as a diffusion source” IEEE Electron Device Letters, vol. 17, p. 88, March 1996. [14]M. Nishida and H. Onodera, “An anomalous increase of threshold voltage with shortening the channel lengths for deeply boron-implanted n-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-28, p.1101, 1981. [15]Tatsuya Kunikiyo, Masato Fujinaga, and Norihiko Kotani, “Reverse short-channel effect due to lateral diffusion of point-defect induced by soyrce/drain ion implantation” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.13, no. 4, April, 1994. [16]Hwang, H. Lee, D.-H. and Hwang, J. M.FET’s “Degradation of MOSFET’s drive current due to halo ion implantion” IEDM Tech. p. 567, 1996. [17]Das, A. De, H. Misra, V. Venkatesan, S. etc. “Effects of halo implants on hots carrier reliability of sub-quarter micron MOSFET’s” IEEE, Annual int. reliability phys.sym., reno, Nevada 1998, p. 189, 1998. [18]Su, J.-G. Huang, C.-T. Wong, S.-C. Cheng, C.-C. Wang C.-C. Huang-Lu, S. and Tsui, B.-Y. “Tilt angle effect on optimizing halo PMOS and NMOS performance” IEEE, Annual int. reliability phys.sym., reno, Nevada 1998, p. 11, 1998. [19]Huang, H. S. Shiu J.-S. and Lin, S.-J. et al. “A modified C-V method used for the Leff and process monitoring of advances 0.15um CMOS device and beyond” Jpn. J. Appl. Phys., vol. 40, p. 1, March 2001. [20]Huang, H. S. Lin, S.-J. and Chen, Y.-J. et al. “A capacitance ratio method used for the Leff extraction of an advanced MOS device with a halo implant” Jpn. J. Appl. Phys., vol. 18, p.953, 2001. [21]ISE TCAD manuals. ISE Integration System Engineering AG, Release 5.
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