在先進CMOS製程中，不論是在元件特性之設計或製程控制之探討上，通道長度都是一個非常重要的元件參數。雖然有許多傳統的有效通道長度淬取方法(I-V方法)已被廣泛的使用，但現今MOS電晶體隨著尺寸的縮小，常使用先進源/汲極製程以得到較好的短通道效能，卻也因此降低了傳統通道長度淬取方法之精確性。在本論文中，我們提出了一個新的C-V量測方法(或稱為”C-R方法)，根據我們所提出的新方法，我們可以有效且精確的淬取出有效通道長度Leff、源/汲極串聯電阻Rsd及閘/汲極電容Cgd等參數。
先進MOS元件通常需要特別的製程(或稱為”源/汲極製程)以得到性能的最佳化。源/汲極製程即是指在源/汲極與通道間之摻雜離子濃度分佈之設計。此製程通常是用來改善元件短通道之效應，卻也會影響有效通道長度之淬取及元件之特性。因此在本論文中，我們將根據C-R方法所淬取出之參數去探討不同源/汲極製程(包含halo implant和germanium implant)對通道長度之影響並使用製程模擬分析之結果驗證我們所提出有效通道長度淬取之C-R方法。
在半導體製程中，由於電腦模擬的速度越來越快且其所需花費較實際製程便宜，因此電腦製程模擬在半導體業界中已逐漸廣泛的使用。若使用有效且精確之模擬軟體，我們即可在短暫的時間內得到精確之模擬結果。在本論文中，我們將使用ISE TCAD模擬軟體去做不同製程之模擬。根據模擬出的不同摻雜濃度分佈之剖面圖，分析其結果與I-V量測數據及C-R方法淬取之參數間的關係，我們可以說明各種源/汲極製程對於元件特性影響及如何作最佳化之調整，並將在此論文中做一完整的介紹。

Channel length of MOSFET’s is one of the most important device parameters to processing technologists and device engineers in their evaluation of process control, device performance and device scaling for next-generation MOS technologies. In a current MOS transistor, advanced process engineering used for obtaining better short channel performance in deep-quarter micro devices will degrade the extraction accuracy of the value of Leff by traditional I-V method. In this thesis, we attended to develop a new extraction method (also named “capacitance-ratio method”) of thin gate oxide parameter extraction for advanced CMOS device.
Advanced MOS devices often need special structures or S/D engineering to optimize their performance. The S/D engineering is referring to the design of dopant impurity distribution between S/D and channel region. This is used to improve the short channel effect, but it will also affect the device characteristic and Leff extraction. Therefore, we investigate the influence of different fabrication process (such as halo tilt angle, halo dose and germanium implant) on explaining the effect of channel characteristic and device performance result from S/D engineering based on C-R method and process simulation.
Recently, process simulations are now as common as circuit simulation for two major reasons: computer simulations are less expensive and much faster than experimental approaches. Using available software, one can simulate all critical process steps in a matter of minutes or hours. According to the simulated device cross-section with doping concentration contours and compare with the analyzed result of C-R method and I-V measured data, it can be a monitor to control S/D process conditions for performance optimization and will be discussed in this thesis.

摘要.......................................................iii
Abstract....................................................iv
誌謝.........................................................v
Contents....................................................vi
Figure Index..............................................viii
Chapter 1 Introduction.......................................1
1.1 Preview...............................................1
1.2 Research Motivation...................................2
1.3 Outline of This Thesis................................4
Chapter 2 Review of Previous Researches......................6
2.1 Various Definitions of Channel Length.................6
2.2 Review of The I-V ("Shift & Ratio")Method.............8
2.2.1 The Principle and Algorithm of the "shift & ratio"
Method................................................8
2.2.2 The Limitations of "shift & ratio" Method.......12
Chapter 3 The Capacitance-Voltage Method Used for Leff
Extraction in Advanced CMOS.......................13
3.1 The Capacitance of a MOS Device......................13
3.1.1 Intrinsic Capacitance...........................14
3.1.2 Parasitic Capacitance...........................15
3.1.3 NMOS Capacitance in Inversion and Accumulation
condition.......................................15
3.2 The Previous C-V ("Decoupled C-V Method") Leff
Extraction Method....................................17
3.3 Algorithm of Modified C-V (Capacitance-Ratio) Method.19
3.3.1 Depletion Compensation Factor...................19
3.3.2 Extracted of Lpb and Lovlap.....................21
3.3.3 Extracted of Cgd and Rsd........................24
3.3.4 Verify of C-R method Using by Simulator.........25
3.3.5 Halo Process Effect on Optimizing NMOS..........28
3.4 S/D Engineering Used for Device Performance Optimize.30
Chapter 4 Theorem and Employ of The Simulation Tool.........32
4.1 The Functions of The ISE TCAD Simulation Tool........33
4.2 Editing The Project of The Process Simulation Tool...34
4.3 Edit The Different Simulation Conditions in Our
Research.............................................36
4.3.1 2D Simulator (DIOS) in ISE TCAD.................36
4.3.2 Different Process Conditions for PMOS...........37
Chapter 5 Results Analysis and Discussion...................41
5.1 Halo Implant Effect of C-R Method and Device
Performance for PMOS.................................41
5.1.1 Optimize of Halo Tilt Angle Effect..............43
5.1.2 Optimize of Halo Dose Effect....................45
5.2 Ge Structure Effect of C-R Method and Device
Performance..........................................50
Chapter 6 Conclusion........................................54
6.1 Conclusion...........................................54
6.2 Further Research.....................................55
Reference...................................................56

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