離散餘弦轉換(DCT)及其反轉換(IDCT)已經被廣泛的運用在許多低位元率的視訊壓縮系統上，而且是許多國際標準的核心部份（如JPEG , MPEG-X , H.26X , …）。在高畫質數位電視及高取樣速率的應用中，高效能的離散餘弦轉換處理器對高品質的多媒體通訊是十分重要的。然而處理離散餘弦轉換所需的計算量非常龐大，所以要得到有效率的二維離散餘弦轉換，我們必須設計出有效率的超大型積體電路(VLSI)晶片來滿足特定影像處理應用技術的即時(real time)需求。本論文提出一個適用於即時影像與視訊系統的高效能二維正反離散餘弦轉換架構，而且以智慧元件(Intellectual property)的觀點，實現此架構於超大型積體電路，以便適用於更多的數位影像編解碼系統上。
本論文從行列分解 (row-column decomposition)的理論架構上加以改良，發展出新的理論架構。由於傳統DCT/IDCT均以乘法器來完成乘法運算，在此我們將採取查表方式取代常係數乘法器，以加快運算速度及節省晶片面積，利用重疊行列運算方式來取代傳統架構所需的矩陣轉置，以及管線式的結構有效地降低整體的計算時間，並達到高推送率的效能。此外，以智慧元件(Intellectual property)的考量，在不同的設計層次加以分析改善，完成整體架構的實現。
在TSMC 0.35um 1P4M製程技術之下，我們使用Compass高性能的標準元件製作此架構，此架構使用了119181個電晶體，晶片面積為4278.4um ´ 4278.4um。而模擬結果顯示本架構之晶片時脈速度可達100MHz，這意味了本架構不但可以應用於許多數位編解碼視訊系統，而且也達到即時(real time)編解碼的要求。

Discrete cosine transform (DCT) has been widely used in the implementation of low bit rate codecs for video compression and becomes an integral part of several international standards (such as JPEG, MPEG-X, H.26X, …). Since DCT takes lots of intensive computations, therefore, it is necessary to realize a cost-effective high speed DCT for video coding in VLSI chip.
In this thesis, we propose a high throughput 2-D DCT/IDCT VLSI architecture for a real-time digital video codec system. Further,we propose to design and implement this DCT/IDCT to an intellectual property (IP) for the digital image data compressing. Besides, a new DCT/IDCT algorithm is developed by using row-column decomposition. We adapt (1) a table look-up method for multiplication can reduce hardware and increase the speed. (2) With a high throughput rate pipelined architecture and (3) row-column overlapped technique is used for this DCT/IDCT. Moreover, IP characteristic is considered in the arithmetic operation of this DCT/IDCT.
Based on TSMC 0.35um 1P4M process parameters, COMPASS, a high performance cell library is for implementation of the proposed architecture. It integrates 119,181 transistors in a 4378.4um ´ 4378.4um chip area. Simulation results show the proposed architecture can work well with 100MHz which meets the requirement of many real-time digital video codec systems.

第一章緒論
1.1以DCT為基礎的視訊壓縮技術…………………………………1
1.2研究動機……………………………………………………….2
1.3本文內容……………………………………………………….3
第二章離散餘弦/反離散餘弦轉換與MPEG-2編解碼系統簡介
2.1 演算法描述…………………………………………………………..4
2.1.1相關研究…………………………………………………………….4
2.1.2二維離散餘弦轉換………………………………………………….9
2.1.3二維反離散餘弦轉換…………………………………………....11
2.2 MPEG-2即時編解碼系統簡介……………………………………….15
2.2.1 MPEG-2編解碼系統……………………………………………….15
2.2.2 Profiles和levels……………………………………………….17
2.2.3系統需求……………………………………………………………18
第三章新架構的離散餘弦轉換
3.1架構設計………………………………………………………………21
3.1.1 傳統架構………………………………………………………….22
3.1.2 新架構說明……………………………………………………….24
3.2 二維離散餘弦轉換………………………………………………….25
3.3 第一級的一維離散餘弦轉換……………………………………….26
3.4 第二級的一維離散餘弦轉換……………………………………….29
3.5 乘法區塊之運算…………………………………………………….33
3.6 計算的準確性……………………………………………………….34
第四章硬體電路設計之概念與方法
4.1 PLA查表電路設計…………………………………………………..36
4.1.1 採用考量………………………………………………………...36
4.1.2 PLA查表電路……………………………………………………..37
4.1.3 PLA的設計流程…………………………………………………..38
4.2 累加運算電路……………………………………………………….45
4.2.1 累加多工器……………………………………………………….45
4.2.2 累加加法器……………………………………………………….45
4.2.3 輔助暫存器……………………………………………………….47
4.3 輸出單元…………………………………………………………….48
4.3.1 路徑多工器……………………………………………………….48
4.3.2 輸出暫存器……………………………………………………….48
4.4 控制電路…………………………………………………………….50
4.4.1 第一級的一維離散餘弦轉換之控制電路……………………….51
4.4.2 第二級的一維離散餘弦轉換之控制電路……………………….53
第五章超大型積體電路晶片設計及模擬結果
5.1 設計流程…………………………………………………………….56
5.2 晶片規格需求……………………………………………………….58
5.3 模擬結果…………………………………………………………….60
5.4 晶片實現結果與比較……………………………………………….61
第六章結論與未來發展
6.1 總結………………………………………………………………….65
6.2 檢討與建議………………………………………………………….67
6.3 未來發展…………………………………………………………….68
參考文獻………………………………………………………………….69

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