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[1] “Video codec for audiovisual services at p´64 kbit/s,” ITU-T Recommendation H.261, Mar. 1993. [2] G. K. Wallace, “The JPEG still picture compression standard,” IEEE Trans. on Consumer Electron., vol. 38, no. 1, pp. xviii — xxxiv, Feb. 1992 [3] “Coding of moving pictures and associated audio,” Committee Draft of Standard ISO 11172-2: ISO/MPEG, Dec. 1991. [4] “Coding of moving pictures and associated audio,” Committee Draft of Standard ISO 13818-2: ISO/MPEG, Dec. 1993. [5] R. Hopkins, “Digital terrestrial HDTV for North America: the grand alliance HDTV system,” IEEE Trans. on Consumer Electron., vol. 40, no. 3, pp. 185-198, Aug. 1994. [6] N. Ahmeed, T. Natarajan, and K. R. Rao, “Discrete cosine transform,” IEEE Trans. on Computer, vol. C-23, pp. 88-93, Jan. 1974. [7] S. Wolter, D. Birreck, and R. Laur, “Classification for 2D-DCTs and a new architecture with distributed arithmetic,” IEEE International Sympoisum on Circuits and Systems, vol. 4, pp. 2204-2207, 1991. [8] M. A. Haque, “A two-dimensional fast cosine transform,” IEEE Trans. on ASSP, vol. 33, no. 6, pp. 1532-1536, Dec. 1985. [9] M. Yan and J. V. McCanny, “VLSI architectures for computing the 2D-DCT,” IEEE International Conference on Systolic Arrays, 1989. [10] M. Vetterli, “Fast 2D discrete cosine transform,” ICASSP 85, pp. 1538-1541.[11] P. Duhamel and C. Guillemot, “Polynomial transform computation of the 2D-DCT,” ICASSP 90, pp. 1515-1518. [12] N. I. Cho and S. U. Lee, “Fast algorithm and implementation of 2D discrete cosine transform,” IEEE Trans. on Circuits and System, vol. 38, no. 3, pp. 297-305, Mar. 1991. [13] N. I. Cho, I. D. Yun, and S. U. Lee, “On the regular structure for the fast 2-D DCT algorithm,” IEEE Trans. on Circuits and System-II: analog and digital signal processing, vol. 43, no. 10, pp. 259-266, Oct. 1996. [14] B. G. Lee, “A new algorithm to compute the discrete cosine transform,” IEEE Trans. on ASSP, vol. ASSP-32, no. 6, pp. 1243-1245, Dec. 1984. [15] H. S. Hou, “A fast recursive algorithm for computing the discrete cosine transform,” IEEE Trans. on ASSP, vol. ASSP-35, no. 10, pp. 1445-1461, Oct. 1987. [16] A. Artieri, E. Macoviak, F. Jutand, and N. Demassieux, “A VLSI one chip for real time two-dimensional discrete cosine transform,” IEEE International Sympoisum on Circuits and Systems, 1988. [17] A. Madisetti and A. N. Willson, Jr., “A 100Mhz 2D 8´8 DCT/IDCT processor for HDTV applications,” IEEE Trans. on Circuit and System for Video Technology, vol. 5, no. 2, pp. 158-165, Apr. 1995. [18] M.-H. Sheu, J.-Y. Lee, J.-F. Wang, A.-N. Suen, and L.-Y. Liu, “A High Throughput-Rate Architecture for 8´8 2-D DCT,” IEEE International Symposium on Circuits and Systems, vol. 3, pp. 1587-1590, May 1993. [19] S. A. White, “Applications of distributed arithmetic to digital sequence Processing: A Tutorial Review,” IEEE ASSP Magazine, pp. 5-19, Jul. 1989. [20] P. N. Tudor, “Tutorial MPEG-2 video compression,” Electric & Communication Engineering Journal, pp. 257-264, Dec. 1995. [21] P. Pirsch and H.-J. Stolberg, “Architectural approaches for video compression,” IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp.176 —185, Jul. 1997. [22] P. Pirsch, N. Demassieux, and W. Gehrke, “VLSI architectures for video compression — a survey,” Proceedings of the IEEE, vol. 83, no. 2, pp. 220-246, Feb. 1995. [23] C.-C. Ju, “A high-throughput DCT/IDCT architecture and design methodology with application to real-time digital video codec system and associated CAD design,” Master Thesis, Nation Chiao-Tung University Electronics Engineering, Taiwan 1995. [24] H.-K. Su, “A DCT/IDCT VLSI architecture for general video applications,” Master Thesis, Nation Chiao-Tung University Electronics Engineering, Taiwan 1998. [25] J. C. Carlach, P. Penard, and J. L. Sicre, “TCAS: A 27Mhz 8´8 discrete cosine transform chip,” ICASSP 89, vol. 4, pp. 23-26, 1989. [26] S.-I. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, H. Terane, and M. Yashimoto, “A 100Mhz 2-D discrete cosine transform core processor,” IEEE J. Solid-State Circuit, vol. 27, no. 4, pp. 492-499, Apr. 1992. [27] M.-H. Sheu, L.-Y. Lee, J.-F. Wang, and L.-Y. Liu, “A high throughput-rate architecture for 8´8 2-D DCT,” ICASSP 93, pp. 1587-1590, 1993. [28] J.-S. Chiang and H.-C. Huang, “Novel architecture for two-dimensional high throughput rate real-time discrete cosine transform and the VLSI design,” Int. J. Electronic, pp. 519-527, 1997. [29] C.-C. Ju and C.-Y. Lee, “A high throughput DCT/IDCT architecture with application to digital video codec system,” The 8th VLSI Design/CAD Symp. Taiwan, pp. 93-96, 1997. [30] S. P. Kim and D. K. Pan, “High modular and concurrent 2-D DCT chip,” ISCAS 92, pp. 1082-1084, 1992. [31] “IEEE standard specifications for the implementation of 8´8 inverse discrete cosine transform,” IEEE Std. 1180-1190, Mar. 1991. [32] T. Miyazaki, “DCT/IDCT processor for HDTV developed with DSP silicon compiler,” J. VLSI Signal Processing, no. 5, pp. 151-158, 1993. [33] M. Matsui, “A 200Mhz 13mm2 2D DCT macrocell using sense-amplifying pipeline flip-flop scheme,” IEEE J. Solid-State Circuit, Vol. 29, No. 12, pp. 1482-1489, Dec. 1994. [34] H. Fujiwara, “An all-ASIC implementation of a low bit-rate video codec,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 2, pp. 123-134, Jun. 1992. [35] V. Srinivasan and K. J. Ray Liu, “VLSI design of high-speed time recursive 2D DCT/IDCT processor for video applications,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 6, no.1, pp. 87-96, Feb. 1996. [36] S.-C. Hsia, B.-D. Liu, J.-F. Yang, and B.-L. Bai, “VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 396-405, Oct. 1995. [37] C.-S. Huang, “The design and implementation of DCT/IDCT chip with novel architecture,” Master Thesis, Tamkang University Electronics Engineering, Taiwan 1999. [38] C.-P. Lin, “The implementation of a novel DCT/IDCT chip,” Master Thesis, Tamkang University Electronics Engineering, Taiwan 2000.
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