臺灣博碩士論文加值系統

為了達到更好的效能，提取大量而有用的指令和資料供給處理核心來執行是很重要的。 而蹤跡，也就是動態指令執行的順序，是一個可提供大量且有效指令的指令提取機制。
最近提出的研究中，以區塊為基礎的蹤跡快取記憶體能提昇每週期指令的產生率(IPC)，其有效的儲存蹤跡快取的空間以暫存並重複使用蹤跡，藉此達到更高的指令平行度。 先將指令以區塊為單位重新命名以儲存在區塊快取記憶體，再利用儲存在蹤跡表內的區塊指標來讀取區塊快取記憶體以建構我們在提取週期所要提供的蹤跡指令。
在２０００年陳淑玲的論文中，提出了一個新的雜湊函數，可達到更高的蹤跡表的命中率。 其預測的下一個蹤跡，是由下一個週期要提取的位址和這個位址所對應的區塊指標(block_id)所雜湊出來。
本篇論文，根據她所提出之架構，使用Verilog硬體描述語言、Debussy偵錯工具、Synthesis電路合成軟體…等，企圖針對此一改良式以區塊為基礎所建立之蹤跡快取機制做硬體電路之設計與實現。

To achieve high performance, the instructions and data must be effectively delivered at high bandwidth to the processing core capable of consuming them.
Trace, dynamic instruction sequence, is a good idea to achieve this goal.
The block-based trace cache (BTC-1999) is a recently proposed solution to gain higher IPC performance.
It buffers and reuses trace with more efficient storage of trace.
The block-based trace cache renames fetch addresses at the basic block level and stores blocks in a block cache.
Traces are constructed by accessing the replicated block caches using block pointer from the trace table.
In her master thesis (EBTC-2000), Ms. Sue-Ling Chen improves the block-based trace cache in fetching trace and provides a new next trace prediction hashing function with higher trace table hit rate.
The predicted next trace identifier is the concatenation of the next cycle fetched PC(FPC) and the next fetch block_id.
In this thesis, based on the architecture Ms. Chen proposed in her thesis, by using Verilog Hardware Design Language, Debussy Bug-detecting tool, Synopsys Synthesis tool,...etc, we attempt to design and implement the enhanced block-based trace cache.

Chapter 1: Introduction ......................................1
1.1: Motivation ..............................................2
1.2: Dynamic instruction sequence---Trace ....................5
1.3: Thesis Organization .....................................6
Chapter 2: Background ........................................7
2.1: Concept of the Block-based Trace Cache (BTC) ............7
2.2: Concept of the Enhanced Block-based Trace Cache (EBTC) .10
Chapter 3: Overall Datapath Diagram of the Enhanced Block-based Trace Cache(EBTC) Architecture ..............................14
3.1: Clock Division .........................................16
3.2: Overall Datapath of the EBTC ...........................27
Chapter 4: Detail Datapath Diagram of Each Component in the EBTC
Architecture ................................................35
4.1: The module FU ..........................................36
4.2 The module RT ...........................................42
4.3 The module TT ...........................................48
4.4 The module BC ...........................................54
4.5 The module COLLAPSE .....................................55
Chapter 5: Functional Verification Results ..................57
5.1 The Block Diagram of the module FU ......................58
5.2 The Block Diagram of the module RT ......................62
5.3 The Block Diagram of the module TT ......................67
5.4 The Block Diagram of the module BC ......................72
5.5 The Block Diagram of the module COLLAPSE ................75
5.6 The Block Diagram of the module EBTC ....................80
Chapter 6: Conclusion and Future Work .......................86

[1] B. Rychlik B. Black and J.P. Shen. The Block-based Trace Cache. In Proceedings of the 26th Annual International Symposium on Computer Architecture(ISCA), pages 196--207, 1999.
[2] Sue-Ling Chen. Performance Evaluation of A Trace Cache Engine.
PhD thesis, Ph.D. thesis, Dept. of Computer Science and Technology, Tatung University, June 2000.
[3] S. Bennett E. Rotenberg and J.E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. In Proceedings of the 29th International Symposium on Microarchitecture(MICRO-29), December 1996.
[4] S. Bennett E. Rotenberg and J.E. Smith. A Trace Cache Microarchitec-ture and Evaluation. In IEEE Transactions on Computers, volume 48, pages 111--120, February 1999.
[5] Y. Sazeides J. Smith E. Rotenberg, Q. Jacobson. Trace Processors. In Computer Sciences Dept. and Dept. of Electrical and Computer Engi-neering. University of Wisconsin, 1997.
[6] S. J. Patel. Delivering Instruction Bandwidth using a Trace Cache. In Ph.D. Dissertation. University of Michigan, 1999.
[7] E. Rotenberg Q. Jacobson and J.E. Smith. Path-based Next Trace Pre-diction. In Proceedings of thirtieth Annual IEEE/ACM International Symposium on Microarchitecture(MICRO-30), pages 14--23, 1997.
[8] N. Jouppi S. Palacharla and J. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th Annual International Symposiumon Computer Architecture(ISCA), pages 206--218, June 1997.
[9] Dezso Sima. Superscalar Instruction Issue. In IEEE Computer Society Circulation Department.
[10] Y.N. Patt S.J. Patel, M. Evers. Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. In Proceedings of the 25th Annual International Symposium on Computer Architecture(ISCA), pages 262--271, 1998.